Verwandte Artikel zu Verification Techniques for System-Level Design
Inhaltsangabe
This book will explain how to verify SoC (Systems on Chip) logic designs using 'formal' and 'semiformal' verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in 'functional' verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity. For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.
Die Inhaltsangabe kann sich auf eine andere Ausgabe dieses Titels beziehen.
Reseña del editor
This book will explain how to verify SoC (Systems on Chip) logic designs using 'formal' and 'semiformal' verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in 'functional' verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity. For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.
Biografía del autor
*Spent 15 years at Fujitsu research laboratories.*Research on synthesis and verification of digital systems for more than 25 years*Full professor at VLSI Design and Education Center in the University of Tokyo
„Über diesen Titel“ kann sich auf eine andere Ausgabe dieses Titels beziehen.
Neu kaufen
Diesen Artikel anzeigen
EUR 124,67
EUR 28,91 für den Versand von Vereinigtes Königreich nach USA
Versandziele, Kosten & Dauer
Suchergebnisse für Verification Techniques for System-Level Design
Beispielbild für diese ISBN
Verification Techniques for System-Level Design
Anbieter: Revaluation Books, Exeter, Vereinigtes Königreich
Verkäuferbewertung 5 von 5 Sternen
Paperback. Zustand: Brand New. 250 pages. 9.25x7.50x0.57 inches. In Stock. Bestandsnummer des Verkäufers zk0124054617
Anzahl: 1 verfügbar