Verilog Styles for Synthesis of Digital Systems - Softcover

Smith, David R; Franzon, Paul D

 
9780201618600: Verilog Styles for Synthesis of Digital Systems
Softcover
ISBN 10: 0201618605 ISBN 13: 9780201618600
Verlag: Pearson, 2000

Inhaltsangabe

For senior/graduate-level courses in Digital Hardware Design/Verilog.

This text is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to students―e.g., synthesis from high-level specifications, and field programmable gate arrays (FPGA) for many applications. The text uses a simpler language (Verilog) and standardizes the methodology to the point where seniors and first-year graduates can get medium complex designs through to gate-level simulation in a single semester.

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The material available within this book is suitable for professionals who have had an introduction to Boolean algebra and computer organization. A working knowledge of Unix and X-windows is necessary, along with some experience with programming languages such as 'C' or Java. The book uses Verilog and standardizing methodology to such a degree that seniors and first year graduate students can see medium complex designs through the gate level simulation in a single semester.

Features:

  • The piece covers style recommendations specifically oriented to synthesis, illustrated with practical working examples, and easily accessible to the reader.
  • It introduces the use of the simulator and then the synthesizers at the earliest practical point; therefore giving the reader the perspective of working with a small design all the way through high level simulation.
  • Large number of examples; from 100-100k gate equivalents.
  • Topics covered include; Synopsys, Altera, Xilinx, and the standard cell.

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Verlag
Pearson
Erscheinungsdatum
2000
Sprache
Englisch
ISBN 10 
0201618605
ISBN 13 
9780201618600
Einband
Taschenbuch
Auflage
1
Anzahl der Seiten
336
Kontakt zum Hersteller
Pearson
https://in.pearson.com/

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Arluno
Milano
20004
Italien