Excerpt from Synthesizing Linear-Array Algorithms From Nested for Loop Algorithms
We will study linear systolic arrays in this paper, as linear arrays are attractive for their bounded i/o requirements and a simple global clock whose rate is independent of the size of the array. We will consider the important class of algorithms structured as (depth) p nested for loops. Vlsi implementation of such algorithms were studied before, but it is our goal to present a systematic method for transforming them into linear arrays.
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