Verwandte Artikel zu Hierarchical Modeling for VLSI Circuit Testing: 89...
Hierarchical Modeling for VLSI Circuit Testing: 89 (The Springer International Series in Engineering and Computer Science) - Hardcover
Inhaltsangabe
Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.
Die Inhaltsangabe kann sich auf eine andere Ausgabe dieses Titels beziehen.
Reseña del editor
Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.
„Über diesen Titel“ kann sich auf eine andere Ausgabe dieses Titels beziehen.
Neu kaufen
Diesen Artikel anzeigen
EUR 76,56
EUR 4,26 für den Versand innerhalb von/der USA
Versandziele, Kosten & DauerWeitere beliebte Ausgaben desselben Titels
Suchergebnisse für Hierarchical Modeling for VLSI Circuit Testing: 89...
Foto des Verkäufers
Hierarchical Modeling for VLSI Circuit Testing (The Kluwer International Series in Engineering and Computer Science)
Anbieter: Antiquariat Bookfarm, Löbnitz, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Hardcover. 1990. 160 Seiten Ehem. Bibliotheksexemplar mit üblichen Merkmalen wie Signatur und Stempel. Moderate Lager- und Gebrauchsspuren. Text bis auf selten mögliche Anstreichungen sauber. Insgesamt guter Zustand. Sprache: englisch. Ex library book with stamps and signature. Slight signs of use. Good condition. Language: english. 9780792390589 Sprache: Englisch Gewicht in Gramm: 939. Bestandsnummer des Verkäufers 1106144
Anzahl: 1 verfügbar
Beispielbild für diese ISBN
Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science, 89)
Anbieter: BOOKWEST, Phoenix, AZ, USA
Verkäuferbewertung 3 von 5 Sternen
Hardcover. Zustand: New. US SELLER SHIPS FAST FROM USA. Bestandsnummer des Verkäufers DOM-136B2-079239058X-HC-2P1-Wht
Anzahl: 1 verfügbar
Beispielbild für diese ISBN
Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science, 89)
Anbieter: Best Price, Torrance, CA, USA
Verkäuferbewertung 5 von 5 Sternen
Zustand: New. SUPER FAST SHIPPING. Bestandsnummer des Verkäufers 9780792390589
Anzahl: 2 verfügbar
Beispielbild für diese ISBN
Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science, 89)
Anbieter: Lucky's Textbooks, Dallas, TX, USA
Verkäuferbewertung 5 von 5 Sternen
Zustand: New. Bestandsnummer des Verkäufers ABLIING23Feb2416190185611
Anzahl: Mehr als 20 verfügbar
Beispielbild für diese ISBN
Hierarchical Modelling for Very Large Scale Integration Circuit Testing (Kluwer International Series in Engineering & Computer Science, Vlsi, Computer Architecture & Digit)
Anbieter: New Book Sale, London, Vereinigtes Königreich
Verkäuferbewertung 5 von 5 Sternen
Hardcover. Zustand: New. Usually Dispatched within 1-2 Business Days , Buy with confidence , excellent customer service. Bestandsnummer des Verkäufers 079239058X--56
Anzahl: 5 verfügbar
Beispielbild für diese ISBN
Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science, 89)
Anbieter: Ria Christie Collections, Uxbridge, Vereinigtes Königreich
Verkäuferbewertung 5 von 5 Sternen
Zustand: New. In. Bestandsnummer des Verkäufers ria9780792390589_new
Anzahl: Mehr als 20 verfügbar
Beispielbild für diese ISBN
Hierarchical Modeling for VLSI Circuit Testing
Print-on-DemandAnbieter: THE SAINT BOOKSTORE, Southport, Vereinigtes Königreich
Verkäuferbewertung 5 von 5 Sternen
Hardback. Zustand: New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 970. Bestandsnummer des Verkäufers C9780792390589
Anzahl: Mehr als 20 verfügbar
Foto des Verkäufers
Hierarchical Modeling for VLSI Circuit Testing
Anbieter: moluna, Greven, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Gebunden. Zustand: New. Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated . Bestandsnummer des Verkäufers 458443287
Anzahl: Mehr als 20 verfügbar
Foto des Verkäufers
Hierarchical Modeling for VLSI Circuit Testing
Anbieter: AHA-BUCH GmbH, Einbeck, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Buch. Zustand: Neu. Neuware - Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models. Bestandsnummer des Verkäufers 9780792390589
Anzahl: 2 verfügbar