Integrated Circuit Defect-Sensitivity: Theory and Computational Models: 208 (The Springer International Series in Engineering and Computer Science) - Hardcover

Pineda De Gyvez, Jose

Hardcover

ISBN 10: 0792393066 ISBN 13: 9780792393061

Verlag: Springer, 1992

Inhaltsangabe

The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC’s). Those fabrication plants would be concentrated with only a few market leaders.

Über diesen Titel

Reseña del editor

Spot defects are random phenomena present in every fabrication line. As technological processes mature towards submicron features, the effect of these defects on the functional and parametric behavior of the IC becomes crucial.
Integrated Circuit Defect-Sensitivity: Theory and Computational Models reviews the importance of a defect-sensitivity analysis in comtemporary VLSI design procedures. The modeling of defects in microelectronics technologies is revised from a set theoretical approach as well as from a practical point of view. This way of handling the material introduces the reader step-by-step to critical area analysis through the construction of formal mathematical models. The rigorous formalism developed in this book is necessary to study the construction of deterministic algorithms for layout defect exploration. Without this basis, it would be impossible to scan layouts in the order of 10 6 objects, or more, in a reasonable time.
The theoretical component of this book is complemented with a set of practical case studies for fault extraction, yield prediction, and IC defect-sensitivity evaluation. These case studies emphasize the fact that by using appropriate formulae combining statistical data with the computed defect-sensitivity, an estimate of the IC's defect tolerance can be obtained at the end of the respective production line. The case studies range from highlighting their geometrical nature as a function of the defect size to more specific situations highlighting layout regions where faults may occur. In addition to the visualization of critical areas, numerical data in the form of tables, graphs and histograms are provided for quantification purposes.
More that, ever smarter, defect-tolerant design strategies have to be devised to attain high yields. Obviously, the work presented in the book is not definitive, and more research will always be useful to advance the field of CAD for manufacturability. This is, of course, one of the interesting challenges imposed by the ever-changing nature of microelectronic technologies. CAD developers and yield practitioners from academia and industry will find that this book lays the foundations for further pioneering work.

Details zur Ausgabe

• Verlag: Springer
• Erscheinungsdatum: 1992
• Sprache: Englisch
• ISBN 10: 0792393066
• ISBN 13: 9780792393061
• Einband: Tapa dura
• Anzahl der Seiten: 196
• Kontakt zum Hersteller: Nicht verfügbar
• Verantwortliche Person: CMN Printpool Inh. Mathis Neumann; https://www.also.com/ec/cms5/en_6000/6000/index.jsp; ; Friedrich-Karl-Str. 9; Hamburg; Deutschland