Book by Joobbani R
Die Inhaltsangabe kann sich auf eine andere Ausgabe dieses Titels beziehen.
Routing of VLSI chips is an important, time consuming, and difficult problem. The difficulty of the problem is attributed to the large number of often conflicting factors that affect the routing quality. Traditional techniques have approached routing by ignoring some of these factors and imposing unnecessary constraints in order to make routing tractable. In addition to the imposition of these restrictions, which simplify the problems to a degree but at the same time reduce the routing quality, traditional approaches use brute force. They often transform the problem into mathematical or graph problems and completely ignore the specific knowledge about the routing task that can greatly help the solution. This thesis overcomes some of the above problems and presents a system that performs routing close to what human designers do. In other words it heavily capitalizes on the knowledge of human expertise in this area, it does not impose unnecessary constraints, it considers all the different factors that affect the routing quality, and most importantly it allows constant user interaction throughout the routing process. To achieve the above, this thesis presents background about some representative techniques for routing and summarizes their characteristics. It then studies in detail the different factors (such as minimum area, number of vias, wire length, etc.) that affect the routing quality, and the different criteria (such as vertical/horizontal constraint graph, merging, minimal rectilinear Steiner tree, etc.) that can be used to optimize these factors.
„Über diesen Titel“ kann sich auf eine andere Ausgabe dieses Titels beziehen.
Gratis für den Versand innerhalb von/der USA
Versandziele, Kosten & DauerEUR 4,41 für den Versand innerhalb von/der USA
Versandziele, Kosten & DauerAnbieter: Friends of the Library Bookstore, Eau Claire, WI, USA
Hardcover. Zustand: Good. No Jacket. A used textbook that has a coffee-colored stain on the top edge. The pages are otherwise clean and unmarked. The spine is slightly cocked and shows some shelf wear on the top and bottom. A few handling marks on the back cover. The corners are sharp. 159 p. "Routing of VLSI chips is an important, time-consuming, and difficult problem. The difficulty of the problem is attributed to the large number of often conflicting factors that affect the routing quality." Not ex-library. Shelf: B-1. Bestandsnummer des Verkäufers 220915JS
Anzahl: 1 verfügbar
Anbieter: Ammareal, Morangis, Frankreich
Hardcover. Zustand: Bon. Ancien livre de bibliothèque. Traces d'usure sur la couverture. Edition 1986. Ammareal reverse jusqu'à 15% du prix net de cet article à des organisations caritatives. ENGLISH DESCRIPTION Book Condition: Used, Good. Former library book. Signs of wear on the cover. Edition 1986. Ammareal gives back up to 15% of this item's net price to charity organizations. Bestandsnummer des Verkäufers E-840-427
Anzahl: 1 verfügbar
Anbieter: Ammareal, Morangis, Frankreich
Hardcover. Zustand: Très bon. Ancien livre de bibliothèque. Légères traces d'usure sur la couverture. Salissures sur la tranche. Edition 1985. Ammareal reverse jusqu'à 15% du prix net de cet article à des organisations caritatives. ENGLISH DESCRIPTION Book Condition: Used, Very good. Former library book. Slight signs of wear on the cover. Stains on the edge. Edition 1985. Ammareal gives back up to 15% of this item's net price to charity organizations. Bestandsnummer des Verkäufers E-573-941
Anzahl: 1 verfügbar
Anbieter: BOOKWEST, Phoenix, AZ, USA
Hardcover. Zustand: New. US SELLER SHIPS FAST FROM USA. Bestandsnummer des Verkäufers 135C2-089838205X
Anzahl: 1 verfügbar
Anbieter: Lucky's Textbooks, Dallas, TX, USA
Zustand: New. Bestandsnummer des Verkäufers ABLIING23Mar2317530032013
Anzahl: Mehr als 20 verfügbar
Anbieter: Ria Christie Collections, Uxbridge, Vereinigtes Königreich
Zustand: New. In. Bestandsnummer des Verkäufers ria9780898382051_new
Anzahl: Mehr als 20 verfügbar
Anbieter: moluna, Greven, Deutschland
Gebunden. Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Routing of VLSI chips is an important, time consuming, and difficult problem. The difficulty of the problem is attributed to the large number of often conflicting factors that affect the routing quality. Traditional techniques have approached routing by ign. Bestandsnummer des Verkäufers 5982383
Anzahl: Mehr als 20 verfügbar
Anbieter: AHA-BUCH GmbH, Einbeck, Deutschland
Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Routing of VLSI chips is an important, time consuming, and difficult problem. The difficulty of the problem is attributed to the large number of often conflicting factors that affect the routing quality. Traditional techniques have approached routing by ignoring some of these factors and imposing unnecessary constraints in order to make routing tractable. In addition to the imposition of these restrictions, which simplify the problems to a degree but at the same time reduce the routing quality, traditional approaches use brute force. They often transform the problem into mathematical or graph problems and completely ignore the specific knowledge about the routing task that can greatly help the solution. This thesis overcomes some of the above problems and presents a system that performs routing close to what human designers do. In other words it heavily capitalizes on the knowledge of human expertise in this area, it does not impose unnecessary constraints, it considers all the different factors that affect the routing quality, and most importantly it allows constant user interaction throughout the routing process. To achieve the above, this thesis presents background about some representative techniques for routing and summarizes their characteristics. It then studies in detail the different factors (such as minimum area, number of vias, wire length, etc.) that affect the routing quality, and the different criteria (such as vertical/horizontal constraint graph, merging, minimal rectilinear Steiner tree, etc.) that can be used to optimize these factors. Bestandsnummer des Verkäufers 9780898382051
Anzahl: 1 verfügbar
Anbieter: THE SAINT BOOKSTORE, Southport, Vereinigtes Königreich
Hardback. Zustand: New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 571. Bestandsnummer des Verkäufers C9780898382051
Anzahl: Mehr als 20 verfügbar
Anbieter: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Deutschland
Buch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Routing of VLSI chips is an important, time consuming, and difficult problem. The difficulty of the problem is attributed to the large number of often conflicting factors that affect the routing quality. Traditional techniques have approached routing by ignoring some of these factors and imposing unnecessary constraints in order to make routing tractable. In addition to the imposition of these restrictions, which simplify the problems to a degree but at the same time reduce the routing quality, traditional approaches use brute force. They often transform the problem into mathematical or graph problems and completely ignore the specific knowledge about the routing task that can greatly help the solution. This thesis overcomes some of the above problems and presents a system that performs routing close to what human designers do. In other words it heavily capitalizes on the knowledge of human expertise in this area, it does not impose unnecessary constraints, it considers all the different factors that affect the routing quality, and most importantly it allows constant user interaction throughout the routing process. To achieve the above, this thesis presents background about some representative techniques for routing and summarizes their characteristics. It then studies in detail the different factors (such as minimum area, number of vias, wire length, etc.) that affect the routing quality, and the different criteria (such as vertical/horizontal constraint graph, merging, minimal rectilinear Steiner tree, etc.) that can be used to optimize these factors. 184 pp. Englisch. Bestandsnummer des Verkäufers 9780898382051
Anzahl: 2 verfügbar