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A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform - Softcover
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A unique ASIC was designed implementing the Haar Wavelet transform for image compression/decompression. ASIC operations include performing the Haar wavelet transform on a 512 by 512 square pixel image, preparing the image for transmission by quantizing and thresholding the transformed data, and performing the inverse Haar wavelet transform, returning the original image with only minor degradation. The ASIC is based on an existing four-chip FPGA implementation. Implementing the design using a dedicated ASIC enhances the speed, decreases chip count to a single die, and uses significantly less power compared to the FPGA implementation. A reduction of RAM accesses was realized and a tradeoff between states and duplication of components for parallel operation were key to the performance gains. Almost half of the external RAM accesses were removed from the FPGA design by incorporating an internal register file. This reduction reduced the number of states needed to process an image increasing the image frame rate by 13% and decreased I/O traffic on the bus by 47%. Adding control lines to the ALU components, thus eliminating unnecessary switching of combination logic blocks, further reduced power requirements. The 22 mm2 ASIC consumes an estimated 430 mW of power when operating at the maximum frequency of 17 MHz.
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A unique ASIC was designed implementing the Haar Wavelet transform for image compression/decompression. ASIC operations include performing the Haar wavelet transform on a 512 by 512 square pixel image, preparing the image for transmission by quantizing and thresholding the transformed data, and performing the inverse Haar wavelet transform, returning the original image with only minor degradation. The ASIC is based on an existing four-chip FPGA implementation. Implementing the design using a dedicated ASIC enhances the speed, decreases chip count to a single die, and uses significantly less power compared to the FPGA implementation. A reduction of RAM accesses was realized and a tradeoff between states and duplication of components for parallel operation were key to the performance gains. Almost half of the external RAM accesses were removed from the FPGA design by incorporating an internal register file. This reduction reduced the number of states needed to process an image increasing the image frame rate by 13% and decreased I/O traffic on the bus by 47%. Adding control lines to the ALU components, thus eliminating unnecessary switching of combination logic blocks, further reduced power requirements. The 22 mm2 ASIC consumes an estimated 430 mW of power when operating at the maximum frequency of 17 MHz.
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A Low Power ApplicationSpecific Integrated Circuit ASIC Implementation of Wavelet TransformInverse Transform
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A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform
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Zustand: New. KlappentextrnrnA unique ASIC was designed implementing the Haar Wavelet transform for image compression/decompression. ASIC operations include performing the Haar wavelet transform on a 512 by 512 square pixel image, preparing the image for tran. Bestandsnummer des Verkäufers 6488453
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A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform
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A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform
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A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform
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Creative Media Partners, LLC Okt 2012, 2012
ISBN 10: 124960026X
ISBN 13: 9781249600268
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Taschenbuch. Zustand: Neu. Neuware - A unique ASIC was designed implementing the Haar Wavelet transform for image compression/decompression. ASIC operations include performing the Haar wavelet transform on a 512 by 512 square pixel image, preparing the image for transmission by quantizing and thresholding the transformed data, and performing the inverse Haar wavelet transform, returning the original image with only minor degradation. The ASIC is based on an existing four-chip FPGA implementation. Implementing the design using a dedicated ASIC enhances the speed, decreases chip count to a single die, and uses significantly less power compared to the FPGA implementation. A reduction of RAM accesses was realized and a tradeoff between states and duplication of components for parallel operation were key to the performance gains. Almost half of the external RAM accesses were removed from the FPGA design by incorporating an internal register file. This reduction reduced the number of states needed to process an image increasing the image frame rate by 13% and decreased I/O traffic on the bus by 47%. Adding control lines to the ALU components, thus eliminating unnecessary switching of combination logic blocks, further reduced power requirements. The 22 mm2 ASIC consumes an estimated 430 mW of power when operating at the maximum frequency of 17 MHz. Bestandsnummer des Verkäufers 9781249600268
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A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform
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A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform
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