CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test: 40 (Frontiers in Electronic Testing) - Hardcover

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9781402083624: CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test: 40 (Frontiers in Electronic Testing)
Hardcover
ISBN 10: 1402083629 ISBN 13: 9781402083624
Verlag: Springer, 2008

Inhaltsangabe

The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.

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Über die Autorin bzw. den Autor

Prof. Sachdev has authored several successful books with Springer

Von der hinteren Coverseite

As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions.

Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired.

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.

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Verlag
Springer
Erscheinungsdatum
2008
Sprache
Englisch
ISBN 10 
1402083629
ISBN 13 
9781402083624
Einband
Tapa dura
Anzahl der Seiten
212
Kontakt zum Hersteller
Nicht verfügbar
Verantwortliche Person
CMN Printpool Inh. Mathis Neumann
https://www.also.com/ec/cms5/en_6000/6000/index.jsp

Friedrich-Karl-Str. 9
Hamburg
Deutschland

Weitere beliebte Ausgaben desselben Titels

9789048178551: CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test: 40 (Frontiers in Electronic Testing)

Vorgestellte Ausgabe

ISBN 10:  904817855X ISBN 13:  9789048178551
Verlag: Springer, 2010
Softcover