Verwandte Artikel zu Planar Double-Gate Transistor
Inhaltsangabe
Until the 1990s, the reduction of the minimum feature sizes used to fabricate in- grated circuits, called "scaling", has highlighted serious advantages as integration density, speed, power consumption, functionality and cost. Direct consequence was the decrease of cost-per-function, so the electronic productivity has largely progressed in this period. Another usually cited trend is the evolution of the in- gration density as expressed by the well-know Moore's Law in 1975: the number of devices per chip doubles every 2 years. This evolution has allowed improving signi?cantly the circuit complexity, offering a great computing power in the case of microprocessor, for example. However, since few years, signi?cant issues appeared such as the increase of the circuit heating, device complexity, variability and dif?culties to improve the integration density. These new trends generate an important growth in development and production costs. Though is it, since 40 years, the evolution of the microelectronics always f- lowed the Moore's law and each dif?culty has found a solution.
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About the Author
Prof. Amara AMARA obtained his HDR (Confirmation of Leading Research Capabilities) from Evry University, a Ph.D. in computer science in 1989 and a DEA (MSc) in 1985 in microelectronics and computer science both from Paris VI University. In 1988 he joined IBM research and development laboratory at Corbeil-Essonnes where he was involved in SRAM memory design with advanced CMOS technologies. From 1989 to 1992, he was assistant professor developing microelectronics academic programs for CEMIP (Microelectronic Center of Paris Iles-de-France) and took part actively to the European Research Project ESPRIT. In 1992, he joined ISEP (Paris Institute for Electronics) in charge of the microelectronics laboratory where he headed a team involved in High Speed GaAs VLSI circuit design. Currently, his research interests are mainly focusing on Low Power circuit design techniques and on Ultra Low Voltage SOI circuits design. In 1999, he did a sabbatical at Stanford University where he joined Professor De Micheli's group. Prof. Amara is in charge of the Electronics and Telecommunications Departments at ISEP and since Marsh 2004 Director of Research. He is member of the Board of Directors of "ISEP-Enterprises" Association, member of the LETI/CEA and ICP (Catholic Institute of Paris) Scientific Committees and member of the CEMIP Executive Committee. He initiated and is General Chair of FTFC, a Low Voltage and Low Power Workshop held every two years in Paris. He is member of many Technical Program Committees, he was member of DATE'04 (Design Automation and Test in Europe) Executive Committee, Guest editor of "Annales des Telecommunications" special edition dedicated to SoC for telecommunication and member of the Microelectronics Journal Editorial Board. He will be the General Chair of ICICDT 2008 in Grenoble and ISCAS 2010 in Paris. Prof. Amara published many papers and gave many invited talks and tutorials all around the world. He is currently President-Elect of the IEEE French section, past Chair (till Marsh 2004) of the IEEE-CAS French Chapter who, under Amara's leadership, was awarded the "2004 Chapter of the Year Award". He is also Counselor of the IEEE ISEP Student Branch.
From the Back Cover
This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and concepts that exploit the electrical features of these new devices and the breakthrough they bring.
Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap.
The book topics are mainly focusing on:
- Detailed description of specific processes that allow the optimization of the CMOS IPDGT device
- CMOS IPDGT modeling, both compact and physical models are presented
- Device characterization
- Design of innovating cells (SRAM cells, basic digital & analog functions) with the objectives to improve the level of integration and the robustness to variability as well as the power consumption optimization, using the degree of freedom introduced by the independent gates.
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