Formal Semantics for VHDL: 307 (The Springer International Series in Engineering and Computer Science) - Softcover

 
9781461359418: Formal Semantics for VHDL: 307 (The Springer International Series in Engineering and Computer Science)
Softcover
ISBN 10: 1461359414 ISBN 13: 9781461359418
Verlag: Springer, 2012

Inhaltsangabe

It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic.
If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations.
Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras.
Formal Semantics for VHDL is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject.

Die Inhaltsangabe kann sich auf eine andere Ausgabe dieses Titels beziehen.

Reseña del editor

It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic.
If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations.
Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras.
Formal Semantics for VHDL is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject.

„Über diesen Titel“ kann sich auf eine andere Ausgabe dieses Titels beziehen.

Verlag
Springer
Erscheinungsdatum
2012
Sprache
Englisch
ISBN 10 
1461359414
ISBN 13 
9781461359418
Einband
Tapa blanda
Anzahl der Seiten
268
Herausgeber
Delgado Kloos Carlos, Breuer P.
Kontakt zum Hersteller
Nicht verfügbar
Verantwortliche Person
CMN Printpool Inh. Mathis Neumann
https://www.also.com/ec/cms5/en_6000/6000/index.jsp

Friedrich-Karl-Str. 9
Hamburg
Deutschland

Weitere beliebte Ausgaben desselben Titels

9780792395522: Formal Semantics for VHDL: 307 (The Springer International Series in Engineering and Computer Science)

Vorgestellte Ausgabe

ISBN 10:  0792395522 ISBN 13:  9780792395522
Verlag: Springer, 1995
Hardcover