The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders.
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Amir Zjajo received the M.Sc. and DIC degrees from the Imperial College London, London, U.K., in 2000 and PhD degree from Eindhoven University of Technology in 2010, all in the electrical engineering. In 2000, he joined Philips Research Laboratories, Eindhoven, The Netherlands, as a member of the research staff in the Mixed-Signal Circuits and Systems Group. From 2006 until 2009, he was with Corporate Research of NXP Semiconductors as a senior research scientist. In 2009, he joined Delft University of Technology as a Faculty member in the Circuit and Systems Group. Dr. Zjajo has published more then 20 papers in referenced journals and conference proceedings, and holds 2 patents with 7 more pending. He serves as a member of Technical Program Committee of IEEE Design, Automation and Test in Europe Conference, and IEEE International Mixed-Signal Circuits, Sensors and Systems Workshop. His research interests include mixed-signal circuit design, signal integrity and timing and yield optimization of VLSI. José Pineda de Gyvez received the Ph.d. degree from the Eindhoven University of Technology, The Netherlands, in 1991. From 1991 until 1999 he was a Faculty member in the Department of Electrical Engineering at Texas A&M University, USA. He is currently a Senior Principal at NXP Semiconductors in The Netherlands. Since 2006 he also holds the professorship "Deep Submicron Integration" in the Department of Electrical Engineering at the Eindhoven University of Technology. Dr. Pineda de Gyvez has been Associate Editor in IEEE Transactions on Circuits and Systems Part I and Part II, and also Associate Editor for Technology in IEEE Transactions on Semiconductor Manufacturing. He is also a member of the editorial board of the Journal of Low Power Electronics. Dr. Pineda has more than 100 combined publications in the fields of testing, nonlinear circuits, and low power design. He is (co)-author of three books, and has a number of grantedpatents. His work has been acknowledged in academic environments as well as in patent portfolios of many companies. Pineda's research has been funded by the Dutch Ministry of Science, US Office of Naval Research, US National Science Foundation, among others. Dr. Pineda is an IEEE Fellow.
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Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the 'silicon foundry' concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders. Bestandsnummer des Verkäufers 9781461363835
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Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the 'silicon foundry' concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders. 196 pp. Englisch. Bestandsnummer des Verkäufers 9781461363835
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Taschenbuch. Zustand: Neu. Integrated Circuit Defect-Sensitivity: Theory and Computational Models | José Pineda de Gyvez | Taschenbuch | The Springer International Series in Engineering and Computer Science | xxiv | Englisch | 2014 | Springer | EAN 9781461363835 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand. Bestandsnummer des Verkäufers 105144008
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Taschenbuch. Zustand: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the 'silicon foundry' concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 196 pp. Englisch. Bestandsnummer des Verkäufers 9781461363835
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