As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.
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Giovanni De Micheli (Ph.D. U.C.Berkely 1983) is Professor and Director of the Institute of Electrical Engineering at Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland and President of the Scientific Committee of CSEM, Neuchâtel, Switzerland. Previously, he was Professor of Electrical Engineering at Stanford University. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis, hw/sw codesign and low-power design, as well as systems on heterogeneous platforms including electrical, micromechanical and biological components. Prof. De Micheli is the recipient of the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems. He is a Fellow of ACM and IEEE. Yusuf Leblebici (Ph.D. U.I.Urbana Champaign 1990) is Professor of Electrical Engineering at EPFL, Lausanne, Switzerland From 1991 to 1993 he worked as Visiting Assistant Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. From 1993 to 1998, he was on the faculty of Istanbul Technical University as Associate Professor of Electrical Engineering. He also worked as a senior designer and project manager at ETA ASIC Design Center, Istanbul. From September 1996 to March 1998, he was an Invited Professor in the Department of Electrical Engineering, at the Swiss Federal Institute of Technology in Lausanne (EPFL). Martin A.M. Gijs (Ph.D. K.U. Leuven 1986) joined the Philips Research Laboratories in Eindhoven, The Netherlands, in 1987, where he worked on micro-and nano-fabrication processes of superconducting Josephson and tunnel junctions, the microfabrication of microstructures in magnetic multilayers showing the giant magnetoresistance effect, the design and realisation of miniaturised motors for hard disk applications and the design and realisation of planar transformers for miniaturised power applications. He joined EPFL in1997 as Professor of Micro Techniques. His present interests are in developing technologies for novel magnetic devices, new microfabrication technologies for microsystems fabrication in general and the development and use of microsystems technologies for microfluidic and biomedical applications in particular. János Vörös (Ph.D. XXX) is an Associate Professor in the Institute for Biomedical Engineering of the University and ETH Zurich heading the Laboratory for Biosensors and Bioelectronics. Prof. Vörös is interested in research and teaching in the areas of Bioelectronics, Nano-Biotechnology, Biosensors, Biophysics, and Biomaterials with special focus on the understanding, monitoring and controlling of molecular and cellular processes at biological interfaces. His research group focuses on the development of novel biosensor techniques for diagnostics and drug discovery; on using nanobiotechnology for interfacing neural networks; as well as on controlling and understanding the behavior of biomolecules and cells in the presence of electrical fields and currents.
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Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation. 236 pp. Englisch. Bestandsnummer des Verkäufers 9781461364290
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Taschenbuch. Zustand: Neu. Hot-Carrier Reliability of MOS VLSI Circuits | Yusuf Leblebici (u. a.) | Taschenbuch | The Springer International Series in Engineering and Computer Science | xvii | Englisch | 2012 | Springer | EAN 9781461364290 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand. Bestandsnummer des Verkäufers 105720981
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Taschenbuch. Zustand: Neu. This item is printed on demand - Print on Demand Titel. Neuware -As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.Springer Nature Customer Service Center GmbH, Europaplatz 3, 69115 Heidelberg 236 pp. Englisch. Bestandsnummer des Verkäufers 9781461364290
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Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation. Bestandsnummer des Verkäufers 9781461364290
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