Verwandte Artikel zu Direct Transistor-Level Layout for Digital Blocks
Inhaltsangabe
Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library.
Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability.
The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout.
Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.
Die Inhaltsangabe kann sich auf eine andere Ausgabe dieses Titels beziehen.
Suchergebnisse für Direct Transistor-Level Layout for Digital Blocks
Beispielbild für diese ISBN
Direct Transistor-Level Layout for Digital Blocks (eng)
Print-on-DemandAnbieter: Brook Bookstore On Demand, Napoli, NA, Italien
Verkäuferbewertung 5 von 5 Sternen
Zustand: new. Questo è un articolo print on demand. Bestandsnummer des Verkäufers SGQSBP40HK
Neu kaufen
EUR 86,24
EUR 4,00 Versand
Versand von Italien nach USA
Versand von Italien nach USA
Anzahl: Mehr als 20 verfügbar
Beispielbild für diese ISBN
Direct Transistor-Level Layout for Digital Blocks
Print-on-DemandAnbieter: Chiron Media, Wallingford, Vereinigtes Königreich
Verkäuferbewertung 5 von 5 Sternen
PF. Zustand: New. This item is printed on demand. Brand new book, sourced directly from publisher. Dispatch time is 6-7 days from our warehouse. Book will be sent in robust, secure packaging to ensure it reaches you securely. Bestandsnummer des Verkäufers 6666-IUK-9781475779516
Neu kaufen
EUR 116,72
EUR 5,39 Versand
Versand von Vereinigtes Königreich nach USA
Versand von Vereinigtes Königreich nach USA
Anzahl: 20 verfügbar
Foto des Verkäufers
Direct Transistor-level Layout for Digital Blocks
Anbieter: GreatBookPrices, Columbia, MD, USA
Verkäuferbewertung 5 von 5 Sternen
Zustand: New. Bestandsnummer des Verkäufers 21734515-n
Neu kaufen
EUR 123,32
EUR 2,37 Versand
Versand innerhalb von USA
Versand innerhalb von USA
Anzahl: 15 verfügbar
Foto des Verkäufers
Direct Transistor-level Layout for Digital Blocks
Anbieter: GreatBookPrices, Columbia, MD, USA
Verkäuferbewertung 5 von 5 Sternen
Zustand: As New. Unread book in perfect condition. Bestandsnummer des Verkäufers 21734515
Gebraucht kaufen
EUR 127,07
EUR 2,37 Versand
Versand innerhalb von USA
Versand innerhalb von USA
Anzahl: 15 verfügbar
Foto des Verkäufers
Direct Transistor-Level Layout for Digital Blocks
Print-on-DemandAnbieter: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout.Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers. 140 pp. Englisch. Bestandsnummer des Verkäufers 9781475779516
Neu kaufen
EUR 106,99
EUR 23,00 Versand
Versand von Deutschland nach USA
Versand von Deutschland nach USA
Anzahl: 2 verfügbar
Foto des Verkäufers
Direct Transistor-Level Layout for Digital Blocks
Print-on-DemandAnbieter: moluna, Greven, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed c. Bestandsnummer des Verkäufers 4207987
Neu kaufen
EUR 92,27
EUR 48,99 Versand
Versand von Deutschland nach USA
Versand von Deutschland nach USA
Anzahl: Mehr als 20 verfügbar
Beispielbild für diese ISBN
Direct Transistor-Level Layout for Digital Blocks
Anbieter: Books Puddle, Woodside, NY, USA
Verkäuferbewertung 4 von 5 Sternen
Zustand: New. pp. 140. Bestandsnummer des Verkäufers 26134195896
Neu kaufen
EUR 155,95
EUR 3,58 Versand
Versand innerhalb von USA
Versand innerhalb von USA
Anzahl: 4 verfügbar
Foto des Verkäufers
Direct Transistor-Level Layout for Digital Blocks
Anbieter: AHA-BUCH GmbH, Einbeck, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout.Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers. Bestandsnummer des Verkäufers 9781475779516
Neu kaufen
EUR 124,85
EUR 35,00 Versand
Versand von Deutschland nach USA
Versand von Deutschland nach USA
Anzahl: 1 verfügbar
Foto des Verkäufers
Direct Transistor-Level Layout for Digital Blocks
Anbieter: preigu, Osnabrück, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Taschenbuch. Zustand: Neu. Direct Transistor-Level Layout for Digital Blocks | Prakash Gopalakrishnan (u. a.) | Taschenbuch | ix | Englisch | 2013 | Springer | EAN 9781475779516 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu. Bestandsnummer des Verkäufers 105124410
Neu kaufen
EUR 95,50
EUR 70,00 Versand
Versand von Deutschland nach USA
Versand von Deutschland nach USA
Anzahl: 5 verfügbar
Foto des Verkäufers
Direct Transistor-Level Layout for Digital Blocks
Verlag:
Springer, Springer Mär 2013, 2013
ISBN 10: 1475779518
ISBN 13: 9781475779516
Neu
Taschenbuch
Anbieter: buchversandmimpf2000, Emtmannsberg, BAYE, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Taschenbuch. Zustand: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 140 pp. Englisch. Bestandsnummer des Verkäufers 9781475779516
Neu kaufen
EUR 106,99
EUR 60,00 Versand
Versand von Deutschland nach USA
Versand von Deutschland nach USA
Anzahl: 1 verfügbar