Functional Verification of Programmable Embedded Architectures: A Top-Down Approach - Softcover

Mishra, Prabhat; Dutt, Nikil D.

Softcover

ISBN 10: 1489973362 ISBN 13: 9781489973368

Verlag: Springer, 2014

Inhaltsangabe

It is widely acknowledged that the cost of validation and testing comprises a s- nificant percentage of the overall development costs for electronic systems today, and is expected to escalate sharply in the future. Many studies have shown that up to 70% of the design development time and resources are spent on functional verification. Functional errors manifest themselves very early in the design flow, and unless they are detected up front, they can result in severe consequence- both financially and from a safety viewpoint. Indeed, several recent instances of high-profile functional errors (e. g. , the Pentium FDIV bug) have resulted in - creased attention paid to verifying the functional correctness of designs. Recent efforts have proposed augmenting the traditional RTL simulation-based validation methodology with formal techniques in an attempt to uncover hard-to-find c- ner cases, with the goal of trying to reach RTL functional verification closure. However, what is often not highlighted is the fact that in spite of the tremendous time and effort put into such efforts at the RTL and lower levels of abstraction, the complexity of contemporary embedded systems makes it difficult to guarantee functional correctness at the system level under all possible operational scenarios. The problem is exacerbated in current System-on-Chip (SOC) design meth- ologies that employ Intellectual Property (IP) blocks composed of processor cores, coprocessors, and memory subsystems. Functional verification becomes one of the major bottlenecks in the design of such systems.

Über diesen Titel

Über die Autorin bzw. den Autor

Farimah Farahmandi is an assistant professor in the Department of Electrical and Computer Engineering at the University of Florida. She received her Ph.D. from the Department of Computer and Information Science and Engineering at the University of Florida, 2018. She received her B.S. and M.S. from the Department of Electrical and Computer Engineering at the University of Tehran, Iran in 2010 and 2013, respectively. Her research interests include design automation of System-on-Chips and energy-efficient systems, formal verification, hardware security validation, and post-silicon validation and debug. Her research has resulted in two books, seven book chapters, and several publications in premier ACM/IEEE journals and conferences including IEEE Transactions on Computers, IEEE Transactions on CAD, Design Automation Conference (DAC), and Design Automation and Test in Europe (DATE). Her research has been recognized by several awards including IEEE System Validation and Debug Technology Committee Student Research Award, Gartner Group Info-Tech Scholarship, a nomination for the Best Paper Award in ASPDAC 2017, and DAC Richard Newton Young Student Fellowship. She has actively collaborated with various research groups (IBM, Intel, and Cisco) that has led to several joint publications. She currently serves as an Associate Editor of IET Computers & Digital Techniques. She also has served on many technical program committees as well as organizing committees of premier ACM and IEEE conferences. Her research has been sponsored by AFRL, DARPA, and Cisco. She is a member of IEEE and ACM. Yuanwen Huang received his Ph.D. degree in Computer Engineering at University of Florida, in 2017. He received his B.E. (Hons.) degree at the Huazhong University of Science and Technology, China, in 2012. His research interests include energy-aware computing, hardware trust validation, system-on-chip verification, and storage and file systems. He has published more than 10papers in peer-reviewed conferences including CCS, DATE, ASPDAC, and ICCD, and transactions including IEEE TCAD, IEEE TIFS and ACM TECS. He received the Best Paper Award from the International Symposium on Quality Electronic Design in 2016. He received the DAC (Design Automation Conference) Richard Newton Young Fellowship award in 2016. He served in the Technical Program Committee for the international conference VLSI Design 2019. He is currently a software engineer at VMware, working on development in storage and file systems. Prabhat Mishra is a Professor in the Department of Computer and Information Science and Engineering at the University of Florida. His research interests include embedded and cyber-physical systems, hardware security and trust, network-on-chip architecture, energy-aware computing, formal verification, system-on-chip validation, and post-silicon debug. He received his Ph.D. in Computer Science and Engineering from the University of California atIrvine in 2004. His research has been recognized by several awards including the NSF CAREER Award, IBM Faculty Award, three Best Paper Awards, and EDAA Outstanding Dissertation Award. Prof. Mishra currently serves as an Associate Editor of ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on VLSI Systems, and Journal of Electronic Testing. He is an ACM Distinguished Scientist and a Senior Member of IEEE.

Von der hinteren Coverseite

Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation. Traditional validation techniques employ different reference models depending on the abstraction level and verification task, resulting in potential inconsistencies between multiple reference models.

This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect’s knowledge about the behavior of the design through architecture specification using an Architecture Description Language (ADL). The authors also address two fundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric.

Functional Verification of Programmable Embedded Architectures: A Top-Down Approach is designed for students, researchers, CAD tool developers, designers, and managers interested in the development of tools, techniques and methodologies for system-level design, microprocessor validation, design space exploration and functional verification of embedded systems.

Details zur Ausgabe

• Verlag: Springer
• Erscheinungsdatum: 2014
• Sprache: Englisch
• ISBN 10: 1489973362
• ISBN 13: 9781489973368
• Einband: Taschenbuch
• Anzahl der Seiten: 200
• Kontakt zum Hersteller: Springer Nature Customer Service Center GmbH; ProductSafety@springernature.com; ; Europaplatz 3; Heidelberg; 69115; Deutschland