Principles of VLSI RTL Design: A Practical Guide - Softcover

Churiwala, Sanjay; Garg, Sapan

Softcover

ISBN 10: 1489995455 ISBN 13: 9781489995452

Verlag: Springer, 2014

Inhaltsangabe

Since register transfer level (RTL) design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains the impact of design decisions taken that may give rise later in the product lifecycle to issues related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc., all which are a function of the way the RTL was originally written. Readers will benefit from a highly practical approach to the fundamentals of these topics, and will be given clear guidance regarding necessary safeguards to observe during RTL design.

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Über die Autorin bzw. den Autor

Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, with two decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx. Sridhar Gangadharan  is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass  RTL Analysis Products at Atrenta. He has over 20 years of experience in the electronic design automation industry. His interest areas include RTL verification, timing closure, delay calculation and memory compilers. He holds a Bachelors degree in Computer Science and Engineering from Indian Institute of Technology in Delhi. He is based in San Jose, CA.

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In the process of integrated circuit design, front-end activities start with a register transfer level (RTL) description, of the functionality desired from the IC.� During subsequent steps in the design flow, issues may arise related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc. which are a function of the way the RTL was originally written.

As a result, RTL designers need to take care of many aspects which can have impact on later steps in the design process. Since RTL design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains those various aspects, their significance, what caution needs to be taken during RTL design and why.� Readers will benefit from a highly practical approach to the fundamentals of uncertainties around functionality, clock domain crossing and clock synchronization, design for test and testability, power consumption, static timing analysis, timing exception handling, and routing congestion.

Hopefully, this book will find its place in the hearts and minds of anyone who
generates RTL code. This includes RTL designers as well as those writing tools
that generate RTL. Relatively new RTL designers will find this book to be a single-source of interesting, rich and useful knowledge.� Experienced RTL designers will be able to appreciate and cement some already known concepts, given the focus on practical situations encountered in real designs.
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* Provides a highly accessible, single-source reference to all key topics essential to an RTL designer;
* Describes in detail specific actions/cautions that designer needs to consider in design to avoid problems in downstream implementation;
* Covers content based on practical experience with numerous real designs from large semiconductor design companies.
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Details zur Ausgabe

• Verlag: Springer
• Erscheinungsdatum: 2014
• Sprache: Englisch
• ISBN 10: 1489995455
• ISBN 13: 9781489995452
• Einband: Taschenbuch
• Anzahl der Seiten: 200
• Kontakt zum Hersteller: ProductSafety@springernature.com; ProductSafety@springernature.com; ; Poststr. 9; Darmstadt; 64293; Deutschland