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Veljko Milutinović (1951) received his PhD from the University of Belgrade in Serbia, spent about a decade on various faculty positions in the USA (mostly at Purdue University and more recently at the University of Indiana in Bloomington), and was a co-designer of the DARPAs pioneering GaAs RISC microprocessor on 200MHz (about a decade before the first commercial effort on that same speed) and was a co-designer also of the related GaAs Systolic Array (with 4096 GaAs microprocessors). Later, for almost three decades, he taught and conducted research at the University of Belgrade in Serbia, for departments of EE, MATH, BA, and PHYS/CHEM. His research is mostly in data mining algorithms and dataflow computing, with the emphasis on mapping of data analytics algorithms onto fast energy efficient architectures. Most of his research was done in cooperation with industry (Intel, Fairchild, Honeywell, Maxeler, HP, IBM, NCR, RCA, etc.). For 20 of his edited books, publication forewords or other contributions were written by 20 different Nobel Laureates with whom he cooperated on his past industry sponsored projects. He published 40 books (mostly in the USA), he has over 100 papers in SCI journals (mostly in IEEE and ACM journals), and he presented invited talks at over 400 destinations worldwide. He has well over 1000 Thomson-Reuters WoS citations, well over 1000 Elsevier SCOPUS citations, and well over 5000 Google Scholar citations. His Google Scholar h index is equal to 40. He is a Life Fellow of the IEEE since 2003 and a Member of The Academy of Europe since 2011. He is a member of the Serbian National Academy of Engineering and a Foreign Member of the Montenegrin National Academy of Sciences and Arts.
Miloš Kotlar received his B.Sc. (2016) and M.Sc. (2017) degrees in Electrical and Computer Engineering from the University of Belgrade, School of Electrical Engineering, Serbia. He is a Ph.D. candidate at the School of Electrical Engineering, University of Belgrade. His general research interests include implementation of energy efficient tensor implementations using the dataflow paradigm (FPGA and ASIC accelerators) and meta learning approaches for anomaly detection tasks.
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