Exploring Memory Hierarchy Design with Emerging Memory Technologies (Lecture Notes in Electrical Engineering, 267, Band 267) - Hardcover

Sun, Guangyu

Hardcover

ISBN 10: 3319006800 ISBN 13: 9783319006802

Verlag: Springer, 2013

Inhaltsangabe

This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, FBDRAM, etc.  The techniques described offer advantages of high density, near-zero static power, and immunity to soft errors, which have the potential of overcoming the “memory wall.”  The authors discuss memory design from various perspectives: emerging memory technologies are employed in the memory hierarchy with novel architecture modification;  hybrid memory structure is introduced to leverage advantages from multiple memory technologies; an analytical model named “Moguls” is introduced to explore quantitatively the optimization design of a memory hierarchy; finally, the vulnerability of the CMPs to radiation-based soft errors is improved by replacing different levels of on-chip memory with STT-RAMs.

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This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, FBDRAM, etc. The techniques described offer advantages of high density, near-zero static power, and immunity to soft errors, which have the potential of overcoming the “memory wall.” The authors discuss memory design from various perspectives: emerging memory technologies are employed in the memory hierarchy with novel architecture modification; hybrid memory structure is introduced to leverage advantages from multiple memory technologies; an analytical model named “Moguls” is introduced to explore quantitatively the optimization design of a memory hierarchy; finally, the vulnerability of the CMPs to radiation-based soft errors is improved by replacing different levels of on-chip memory with STT-RAMs.

· Provides a holistic study of using emerging memory technologies in different levels of the memory hierarchy;

· Equips readers with techniques for memory design with improved performance, energy consumption, and reliability;

· Includes coverage of all memory levels, ranging from cache to storage;

· Explains how to choose the proper memory technologies in different levels of the memory hierarchy.

Details zur Ausgabe

• Verlag: Springer
• Erscheinungsdatum: 2013
• Sprache: Englisch
• ISBN 10: 3319006800
• ISBN 13: 9783319006802
• Einband: Gebundene Ausgabe
• Anzahl der Seiten: 129
• Kontakt zum Hersteller: Springer Nature Customer Service Center GmbH; ProductSafety@springernature.com; ; Europaplatz 3,69115 Heidelberg, Germany; Heidelberg; 69115; Deutschland