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Algorithm Engineering and Experimentation: International Workshop ALENEX'99 Baltimore, MD, USA, January 15-16, 1999, Selected Papers (Lecture Notes in Computer Science, 1619, Band 1619) - Softcover

 
9783540662273: Algorithm Engineering and Experimentation: International Workshop ALENEX'99 Baltimore, MD, USA, January 15-16, 1999, Selected Papers (Lecture Notes in Computer Science, 1619, Band 1619)
Softcover
ISBN 10: 3540662278 ISBN 13: 9783540662273
Verlag: Springer, 2008

Inhaltsangabe

Symmetric multiprocessors (SMPs) dominate the high-end server market and are currently the primary candidate for constructing large scale multiprocessor systems. Yet, the design of e cient parallel algorithms for this platform c- rently poses several challenges. The reason for this is that the rapid progress in microprocessor speed has left main memory access as the primary limitation to SMP performance. Since memory is the bottleneck, simply increasing the n- ber of processors will not necessarily yield better performance. Indeed, memory bus limitations typically limit the size of SMPs to 16 processors. This has at least twoimplicationsfor the algorithmdesigner. First, since there are relatively few processors availableon an SMP, any parallel algorithm must be competitive with its sequential counterpart with as little as one processor in order to be r- evant. Second, for the parallel algorithm to scale with the number of processors, it must be designed with careful attention to minimizing the number and type of main memory accesses. In this paper, we present a computational model for designing e cient al- rithms for symmetric multiprocessors. We then use this model to create e cient solutions to two widely di erent types of problems - linked list pre x com- tations and generalized sorting. Both problems are memory intensive, but in die rent ways. Whereas generalized sorting algorithms typically require a large numberofmemoryaccesses, they areusuallytocontiguousmemorylocations. By contrast, prex computation algorithms typically require a more modest qu- tity of memory accesses, but they are are usually to non-contiguous memory locations.

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Über die Autorin bzw. den Autor

Catherine C. McGeoch earned her Ph.D. in computer science from Carnegie Mellon University in 1986. She joined the faculty of Amherst College in 1987, where she is presently the Beitzel Professor of Technology and Society and past chair of the computer science department. Starting in summer 2014, she has taken a leave of absence from the college to work at D-Wave Systems Inc. Her research interests center around the development of methods and techniques for experimental analysis of algorithms, with special emphasis on algorithms and heuristics for NP-Hard problems. She co-founded the DIMACS Challenges with David S. Johnson, and co-founded the annual workshops on Algorithm Engineering and Experimentation (ALENEX), with Michael Goodrich. She is past Editor in Chief of the ACM Journal of Experimental Algorithmics, and currently a member of the ACM publications board. She is the author of A Guide to Experimental Algorithmics, published in 2012.

Von der hinteren Coverseite

Symmetric multiprocessors (SMPs) dominate the high-end server market and are currently the primary candidate for constructing large scale multiprocessor systems. Yet, the design of e cient parallel algorithms for this platform c- rently poses several challenges. The reason for this is that the rapid progress in microprocessor speed has left main memory access as the primary limitation to SMP performance. Since memory is the bottleneck, simply increasing the n- ber of processors will not necessarily yield better performance. Indeed, memory bus limitations typically limit the size of SMPs to 16 processors. This has at least twoimplicationsfor the algorithmdesigner. First, since there are relatively few processors availableon an SMP, any parallel algorithm must be competitive with its sequential counterpart with as little as one processor in order to be r- evant. Second, for the parallel algorithm to scale with the number of processors, it must be designed with careful attention to minimizing the number and type of main memory accesses. In this paper, we present a computational model for designing e cient al- rithms for symmetric multiprocessors. We then use this model to create e cient solutions to two widely di erent types of problems - linked list pre x com- tations and generalized sorting. Both problems are memory intensive, but in die rent ways. Whereas generalized sorting algorithms typically require a large numberofmemoryaccesses, they areusuallytocontiguousmemorylocations. By contrast, prex computation algorithms typically require a more modest qu- tity of memory accesses, but they are are usually to non-contiguous memory locations.

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Verlag
Springer
Erscheinungsdatum
2008
Sprache
Englisch
ISBN 10 
3540662278
ISBN 13 
9783540662273
Einband
Taschenbuch
Anzahl der Seiten
364
Herausgeber
Goodrich Michael T., McGeoch Catherine C.
Kontakt zum Hersteller
Nicht verfügbar
Verantwortliche Person
Nicht verfügbar