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Source Level Debugging of Verilog Designs: Automated Source Level Debugging of HDL Designs - Softcover
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Debugging is a very crucial part of hardware design cycle. Once a design is completed, all the possible faults need to be located and corrected. Although the complexity of hardware design is ever increasing, debugging is still mostly performed manually. Today, debugging has become a very painstaking and time consuming task. Model-based diagnosis provides a solid foundation for automated debugging and fault localization but sometimes the quality of the results is questionable as too many diagnosis candidates are reported. The work presented in this book shows how to apply model-based diagnosis to debugging of synthesizable Verilog designs. Moreover, Two extensions of the model based debugging theory to improve the debugging process in terms of reduction in the number of diagnosis candidates reported, are proposed.
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Debugging is a very crucial part of hardware design cycle. Once a design is completed, all the possible faults need to be located and corrected. Although the complexity of hardware design is ever increasing, debugging is still mostly performed manually. Today, debugging has become a very painstaking and time consuming task. Model-based diagnosis provides a solid foundation for automated debugging and fault localization but sometimes the quality of the results is questionable as too many diagnosis candidates are reported. The work presented in this book shows how to apply model-based diagnosis to debugging of synthesizable Verilog designs. Moreover, Two extensions of the model based debugging theory to improve the debugging process in terms of reduction in the number of diagnosis candidates reported, are proposed.
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Source Level Debugging of Verilog Designs : Automated Source Level Debugging of HDL Designs
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VDM Verlag Dr. Müller e.K., 2010
ISBN 10: 3639262875
ISBN 13: 9783639262872
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Source Level Debugging of Verilog Designs | Automated Source Level Debugging of HDL Designs
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Taschenbuch. Zustand: Neu. Source Level Debugging of Verilog Designs | Automated Source Level Debugging of HDL Designs | Naveed Riaz | Taschenbuch | Deutsch | VDM Verlag Dr. Müller | EAN 9783639262872 | Verantwortliche Person für die EU: VDM Verlag Dr. Müller, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu. Bestandsnummer des Verkäufers 101069846
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Source Level Debugging of Verilog Designs
Verlag:
VDM Verlag Dr. Müller, 2010
ISBN 10: 3639262875
ISBN 13: 9783639262872
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Kartoniert / Broschiert. Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Riaz NaveedNaveed Riaz received a Ph.D. from Graz University of Technology (2008) in Software Engineering, a M.S. in Software Engineering (2005) from National University of Sciences and Technology (NUST), Rawalpindi, Pakistan and a M. Bestandsnummer des Verkäufers 4972041
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