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Buchbeschreibung Zustand: New. Bestandsnummer des Verkäufers ABLIING23Mar3113020268841
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Buchbeschreibung Zustand: New. PRINT ON DEMAND Book; New; Fast Shipping from the UK. No. book. Bestandsnummer des Verkäufers ria9783659180767_lsuk
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Buchbeschreibung PF. Zustand: New. Bestandsnummer des Verkäufers 6666-IUK-9783659180767
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Buchbeschreibung PAP. Zustand: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Bestandsnummer des Verkäufers L0-9783659180767
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Buchbeschreibung Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The book investigates test vector reordering algorithm for minimizing the power dissipation during testing of VLSI circuits. Testing plays a key role in design flow and is the major challenging task for design and test engineers. Power dissipation is critical problem during testing phase. The test vectors generated from Automatic Test Pattern Generator used for testing are statistically independent which leads to more power dissipation. The testing power can be reduced by reordering the sequence of test vectors. The reordering algorithm is developed using the graph theory with heuristic concept to find more sub-optimal solutions. Five functional metrics such as Cosine, Hamming, Mahalanobis, Minkowski and Seuclidean are considered for reordering the test vectors. Don't care replacement method is also proposed for reordered test set to reduce further the transitions in the CUT. Both the methods are implemented and simulated in ISCAS85 benchmark circuits to evaluate the transitions and average power. The results show that transitions and average power are reduced considerably for functions other than hamming distance when compared with unordered test set and existing methods. 76 pp. Englisch. Bestandsnummer des Verkäufers 9783659180767
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Buchbeschreibung Taschenbuch. Zustand: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The book investigates test vector reordering algorithm for minimizing the power dissipation during testing of VLSI circuits. Testing plays a key role in design flow and is the major challenging task for design and test engineers. Power dissipation is critical problem during testing phase. The test vectors generated from Automatic Test Pattern Generator used for testing are statistically independent which leads to more power dissipation. The testing power can be reduced by reordering the sequence of test vectors. The reordering algorithm is developed using the graph theory with heuristic concept to find more sub-optimal solutions. Five functional metrics such as Cosine, Hamming, Mahalanobis, Minkowski and Seuclidean are considered for reordering the test vectors. Don't care replacement method is also proposed for reordered test set to reduce further the transitions in the CUT. Both the methods are implemented and simulated in ISCAS85 benchmark circuits to evaluate the transitions and average power. The results show that transitions and average power are reduced considerably for functions other than hamming distance when compared with unordered test set and existing methods. Bestandsnummer des Verkäufers 9783659180767
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Buchbeschreibung PAP. Zustand: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Bestandsnummer des Verkäufers L0-9783659180767
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