Low Power Phase Locked Loop With Multiple Output Using VLSI Technology - Softcover

Belorkar, Ujwala A.; Ladhake, Siddharth A.

Softcover

ISBN 10: 3659329258 ISBN 13: 9783659329258

Verlag: LAP LAMBERT Academic Publishing, 2013

Inhaltsangabe

DESIGN AND ANALYSIS OF PHASE LOCKED LOOP WITH MULTIPLE OUTPUT USING VLSI TECHNOLOGY Dr.Ujwala A. Belorkar,Dr.Siddharth A. Ladhake. Efforts has been taken to design Low Power, phase locked loop with multiple output, using 45nm VLSI technology. The design process, at various levels, is usually evolutionary in nature. It starts with a given set of requirement. When the requirements are not met, the design has to be improved.The proposed PLL is designed and analysed using 45 nm CMOS/VLSI technology with microwind 3.1. The effective gate length required for 45 nm technology is 25nm. Low Power (0.211mwatt) phase locked loop with four multiple outputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz,1.65 GHz, 0.825 GHz, and 0.412 GHz respectively is obtained using 45 nm VLSI technology. Thus a very high efficient, optimum area chip is designed and analysed for phase locked loop with low power of 0.211 mw and four multiple outputs.

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Über die Autorin bzw. den Autor

Ms. Ujwala A. Belorkar ,M.E.[Digital Electronics],Ph.D.[Electronics Engineering]Ms. Ujwala A. Belorkar working as a Professor & Head of Electronics & Telecommunication Department at H.V.P.M's College of Engineering & Technology, Amravati. Her research area is Micro Electronic Systems Design using VLSI Technology.

Details zur Ausgabe

• Verlag: LAP LAMBERT Academic Publishing
• Erscheinungsdatum: 2013
• Sprache: Englisch
• ISBN 10: 3659329258
• ISBN 13: 9783659329258
• Einband: Taschenbuch
• Anzahl der Seiten: 96
• Kontakt zum Hersteller: Nicht verfügbar
• Verantwortliche Person: AV Akademikerverlag; customerservice@vdm-vsg.de; ; Brivibas gatve 197; Riga; 1039; Lettland