Verwandte Artikel zu The Dynamic Vedic Multiplier Implemented in FPGA for...

The Dynamic Vedic Multiplier Implemented in FPGA for DSP applications: High speed digital design - Softcover

Gurumoorthy, Vaithiyanathan; K., Venkatesan; S., Sivaramakrishnan

 
9783659353598: The Dynamic Vedic Multiplier Implemented in FPGA for DSP applications: High speed digital design

Inhaltsangabe

Now-a-days an interest in the Vedic system is growing well in technology next to education. Developing a effective algorithim for VLSI from Vedic Mathematical Sutras(Formulae) in calculus, computing, square, Cube etc. Sri Bharati Krsna Tirthaji (1884-1960) has given the complete mathematical calculations in a easiest way ever. But the real beauty of Vedic Mathematics cannot be fully appreciated without used it in a technology Properly. One can then see that it is perhaps the most refined and efficient mathematical system which implemented in the digital signal application. This initiative work should be extended up-to a practical application. Constructive criticisms and suggestions from researchers and student scholars regarding this book are welcome. -B.Divya

Die Inhaltsangabe kann sich auf eine andere Ausgabe dieses Titels beziehen.

Über die Autorin bzw. den Autor

Mr.Vaithi Guru,Pursuing his Bachelor of Engineering in Department of EIE,Adhiyamaan College of Engineering,Hosur,TN,India.He published three international journal papers and presented several papers in national/international conferences,He has interested in the research areas VLSI,Digital electronics,Process Control&Industrial Instrumentation.

„Über diesen Titel“ kann sich auf eine andere Ausgabe dieses Titels beziehen.