Verwandte Artikel zu Memory Subsystem in Multicore Architectures: Design...
Memory Subsystem in Multicore Architectures: Design and analysis of a coherent memory subsystem for FPGA-based multicore embedded systems - Softcover
Inhaltsangabe
Cache coherency and memory consistency are of the most decisive and challenging issues in the design of shared-memory multi-core systems that influence both the correctness and performance of parallel programs. In this book, we identify and analyze the problem of designing a coherent/consistent memory subsystem in general and then focus on FPGA-based multi-core embedded systems containing general purpose CPU's and dedicated hardware accelerators. We narrow down the range of the problem by targeting only the stream-based applications and developing dedicated application-specific solutions. A flexible Windowed-FIFO communication pattern is proposed to be used by the parallel programs being run on the multi-core system. The software APIs for the FPGA platform are implemented and tested, a customized streaming cache memory is designed, implemented and tested based on the proposed communication pattern and in the end, example embedded systems are developed and tested on the FPGA platform to prove the correct functionality of the APIs, the cache memory and the coherent data communication between the cores.
Die Inhaltsangabe kann sich auf eine andere Ausgabe dieses Titels beziehen.
Reseña del editor
Cache coherency and memory consistency are of the most decisive and challenging issues in the design of shared-memory multi-core systems that influence both the correctness and performance of parallel programs. In this book, we identify and analyze the problem of designing a coherent/consistent memory subsystem in general and then focus on FPGA-based multi-core embedded systems containing general purpose CPU's and dedicated hardware accelerators. We narrow down the range of the problem by targeting only the stream-based applications and developing dedicated application-specific solutions. A flexible Windowed-FIFO communication pattern is proposed to be used by the parallel programs being run on the multi-core system. The software APIs for the FPGA platform are implemented and tested, a customized streaming cache memory is designed, implemented and tested based on the proposed communication pattern and in the end, example embedded systems are developed and tested on the FPGA platform to prove the correct functionality of the APIs, the cache memory and the coherent data communication between the cores.
Biografía del autor
I was born in Tehran, Iran in 1979.After my bachelor in hardwareengineering, I worked formore than 6 years in Iran,Malaysia and Netherlands as adigital system design and verificationengineer. I then joinedTUDelft and completedmy master in embedded systems in 2011.I went back to industry andhave been working on digital systemsever since.
„Über diesen Titel“ kann sich auf eine andere Ausgabe dieses Titels beziehen.
- VerlagLAP LAMBERT Academic Publishing
- Erscheinungsdatum2014
- ISBN 10 3659636819
- ISBN 13 9783659636813
- EinbandTapa blanda
- SpracheEnglisch
- Anzahl der Seiten172
- Kontakt zum HerstellerNicht verfügbar
EUR 112,35
EUR 29,64 für den Versand von Vereinigtes Königreich nach Deutschland
Versandziele, Kosten & DauerNeu kaufen
Diesen Artikel anzeigen
EUR 43,20
Gratis für den Versand innerhalb von/der Deutschland
Versandziele, Kosten & DauerSuchergebnisse für Memory Subsystem in Multicore Architectures: Design...
Foto des Verkäufers
Memory Subsystem in Multicore Architectures
Verlag:
LAP LAMBERT Academic Publishing, 2014
ISBN 10: 3659636819
ISBN 13: 9783659636813
Neu
Softcover
Anbieter: moluna, Greven, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Roostaie VahidI was born in Tehran, Iran in 1979.After my bachelor in hardwareengineering, I worked formore than 6 years in Iran,Malaysia and Netherlands as adigital system design and verificationengineer. I then joinedTUDelft and co. Bestandsnummer des Verkäufers 5170117
Anzahl: Mehr als 20 verfügbar
Foto des Verkäufers
Memory Subsystem in Multicore Architectures
Verlag:
LAP LAMBERT Academic Publishing Nov 2014, 2014
ISBN 10: 3659636819
ISBN 13: 9783659636813
Neu
Taschenbuch
Anbieter: buchversandmimpf2000, Emtmannsberg, BAYE, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Taschenbuch. Zustand: Neu. Neuware -Cache coherency and memory consistency are of the most decisive and challenging issues in the design of shared-memory multi-core systems that influence both the correctness and performance of parallel programs. In this book, we identify and analyze the problem of designing a coherent/consistent memory subsystem in general and then focus on FPGA-based multi-core embedded systems containing general purpose CPU's and dedicated hardware accelerators. We narrow down the range of the problem by targeting only the stream-based applications and developing dedicated application-specific solutions. A flexible Windowed-FIFO communication pattern is proposed to be used by the parallel programs being run on the multi-core system. The software APIs for the FPGA platform are implemented and tested, a customized streaming cache memory is designed, implemented and tested based on the proposed communication pattern and in the end, example embedded systems are developed and tested on the FPGA platform to prove the correct functionality of the APIs, the cache memory and the coherent data communication between the cores.Books on Demand GmbH, Überseering 33, 22297 Hamburg 172 pp. Englisch. Bestandsnummer des Verkäufers 9783659636813
Anzahl: 2 verfügbar
Foto des Verkäufers
Memory Subsystem in Multicore Architectures : Design and analysis of a coherent memory subsystem for FPGA-based multicore embedded systems
Verlag:
LAP LAMBERT Academic Publishing, 2014
ISBN 10: 3659636819
ISBN 13: 9783659636813
Neu
Taschenbuch
Anbieter: AHA-BUCH GmbH, Einbeck, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Taschenbuch. Zustand: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Cache coherency and memory consistency are of the most decisive and challenging issues in the design of shared-memory multi-core systems that influence both the correctness and performance of parallel programs. In this book, we identify and analyze the problem of designing a coherent/consistent memory subsystem in general and then focus on FPGA-based multi-core embedded systems containing general purpose CPU's and dedicated hardware accelerators. We narrow down the range of the problem by targeting only the stream-based applications and developing dedicated application-specific solutions. A flexible Windowed-FIFO communication pattern is proposed to be used by the parallel programs being run on the multi-core system. The software APIs for the FPGA platform are implemented and tested, a customized streaming cache memory is designed, implemented and tested based on the proposed communication pattern and in the end, example embedded systems are developed and tested on the FPGA platform to prove the correct functionality of the APIs, the cache memory and the coherent data communication between the cores. Bestandsnummer des Verkäufers 9783659636813
Anzahl: 1 verfügbar
Foto des Verkäufers
Memory Subsystem in Multicore Architectures
Verlag:
LAP LAMBERT Academic Publishing Nov 2014, 2014
ISBN 10: 3659636819
ISBN 13: 9783659636813
Neu
Taschenbuch
Anbieter: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Cache coherency and memory consistency are of the most decisive and challenging issues in the design of shared-memory multi-core systems that influence both the correctness and performance of parallel programs. In this book, we identify and analyze the problem of designing a coherent/consistent memory subsystem in general and then focus on FPGA-based multi-core embedded systems containing general purpose CPU's and dedicated hardware accelerators. We narrow down the range of the problem by targeting only the stream-based applications and developing dedicated application-specific solutions. A flexible Windowed-FIFO communication pattern is proposed to be used by the parallel programs being run on the multi-core system. The software APIs for the FPGA platform are implemented and tested, a customized streaming cache memory is designed, implemented and tested based on the proposed communication pattern and in the end, example embedded systems are developed and tested on the FPGA platform to prove the correct functionality of the APIs, the cache memory and the coherent data communication between the cores. 172 pp. Englisch. Bestandsnummer des Verkäufers 9783659636813
Anzahl: 2 verfügbar
Beispielbild für diese ISBN
Memory Subsystem in Multicore Architectures: Design and analysis of a coherent memory subsystem for FPGA-based multicore embedded systems
Verlag:
LAP LAMBERT Academic Publishing, 2014
ISBN 10: 3659636819
ISBN 13: 9783659636813
Gebraucht
Paperback
Anbieter: Mispah books, Redhill, SURRE, Vereinigtes Königreich
Verkäuferbewertung 4 von 5 Sternen
Paperback. Zustand: Like New. Like New. book. Bestandsnummer des Verkäufers ERICA77336596368196
Anzahl: 1 verfügbar