Variability Tolerant Networks on Chip - Softcover

Gawish, Eman

Softcover

ISBN 10: 3659660906 ISBN 13: 9783659660900

Verlag: LAP LAMBERT Academic Publishing, 2015

Inhaltsangabe

NoC have been successfully replacing interconnects in multi-core chip. As technology scales down, process variations cause NoC links designed to be identical to have different electrical properties. We propose statistical design methodology that uses a statistical guard to tolerate variations with lower guard than conventional worst-case design. Thus saving power at low failure rate. A variability-aware NoC topology and geometry scaling, in addition to topology evaluation from variation perspective help the designer to perform scaling and choose the topology with lower variations for different technology nodes and NoC size. Finally, variability-aware routing algorithms make use of process variability link failure probability and adapt routing to reduce the NoC failure rate.

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Über die Autorin bzw. den Autor

Eman Kamel Gawish received the Ph.D. in Electronics and Electrical Communications Engineering from Cairo University, Giza, Egypt, in 2013. Her general research interests are in advanced system architectures, especially networks-on-chip, VLSI design, fabrication process variability, CAD tools, modelling and simulation.

Details zur Ausgabe

• Verlag: LAP LAMBERT Academic Publishing
• Erscheinungsdatum: 2015
• Sprache: Englisch
• ISBN 10: 3659660906
• ISBN 13: 9783659660900
• Einband: Taschenbuch
• Anzahl der Seiten: 132
• Kontakt zum Hersteller: Nicht verfügbar
• Verantwortliche Person: SIA OmniScriptum Publishing; customerservice@vdm-vsg.de; ; Brivibas gatve 197; Riga; 1039; Lettland