Design of Magnitude Comparator Using Reversible Logic Gates - Softcover

Karunamurthi, Saranya; Thangavel, Saranya; Boopalan, Saravana Priya

Softcover

ISBN 10: 3659796069 ISBN 13: 9783659796067

Verlag: LAP LAMBERT Academic Publishing, 2018

Inhaltsangabe

A need for low power ICs arises to keep the power density of ICs within tolerable limits. While the power dissipation increases linearly with advanced version processors, the power density also increases exponentially, because of the ever-shrinking size of the integrated circuits. Reversible logic is emerging as an important research area in the recent years due to its ability to reduce power dissipation, which is the main requirement in low power digital design.In our proposed method reversible comparator based on CMOS logic circuit is designed using reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The experimental results obtained for implementation in CADENCE EDA 180nm technology shows the considerable reduction in terms of Power Delay Product in comparison with the comparator designed in conventional.

Über diesen Titel

Über die Autorin bzw. den Autor

Mrs. Saranya Karunamurthi is working as an Assistant Professor, Department of EEE in Dr. Mahalingam College of Engineering & Technology, Pollachi, Tamil Nadu, India. She completed her Master Degree in Applied Electronics under Anna University. Her research interests are VLSI Design, Analog & Digital Circuits, Reversible logics, ASIC Implementation.

Details zur Ausgabe

• Verlag: LAP LAMBERT Academic Publishing
• Erscheinungsdatum: 2018
• Sprache: Englisch
• ISBN 10: 3659796069
• ISBN 13: 9783659796067
• Einband: Taschenbuch
• Anzahl der Seiten: 60
• Kontakt zum Hersteller: Nicht verfügbar
• Verantwortliche Person: SIA OmniScriptum Publishing; customerservice@vdm-vsg.de; ; Brivibas gatve 197; Riga; 1039; Lettland