Verwandte Artikel zu Cost-effective Methods for High-speed Nanometer CMOS...
Cost-effective Methods for High-speed Nanometer CMOS VLSI Design: Interconnect and Circuits - Softcover
Inhaltsangabe
The semiconductor industry has been following Moore?s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.
Die Inhaltsangabe kann sich auf eine andere Ausgabe dieses Titels beziehen.
Reseña del editor
The semiconductor industry has been following Moore's law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.
Biografía del autor
Charbel Akl received a M.S. in Computer Engineering from University of Balamand, Lebanon, in 2004, and a PhD in Computer Engineering from University of Louisiana at Lafayette in 2008. After graduation, he joined Intel Corporation where he is currently working on the design and implementation of low power microprocessors.
„Über diesen Titel“ kann sich auf eine andere Ausgabe dieses Titels beziehen.
EUR 119,31
EUR 28,67 für den Versand von Vereinigtes Königreich nach USA
Versandziele, Kosten & DauerNeu kaufen
Diesen Artikel anzeigen
EUR 59,00
EUR 23,00 für den Versand von Deutschland nach USA
Versandziele, Kosten & DauerSuchergebnisse für Cost-effective Methods for High-speed Nanometer CMOS...
Foto des Verkäufers
Cost-effective Methods for High-speed Nanometer CMOS VLSI Design
Verlag:
LAP LAMBERT Academic Publishing Mai 2010, 2010
ISBN 10: 3838307321
ISBN 13: 9783838307329
Neu
Taschenbuch
Anbieter: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The semiconductor industry has been following Moore s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs. 132 pp. Englisch. Bestandsnummer des Verkäufers 9783838307329
Anzahl: 2 verfügbar
Foto des Verkäufers
Cost-effective Methods for High-speed Nanometer CMOS VLSI Design
Verlag:
LAP LAMBERT Academic Publishing, 2010
ISBN 10: 3838307321
ISBN 13: 9783838307329
Neu
Softcover
Anbieter: moluna, Greven, Deutschland
Verkäuferbewertung 4 von 5 Sternen
Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Akl CharbelCharbel Akl received a M.S. in Computer Engineering from University of Balamand, Lebanon, in 2004, and a PhD in Computer Engineering from University of Louisiana at Lafayette in 2008. After graduation, he joined Intel . Bestandsnummer des Verkäufers 5411448
Anzahl: Mehr als 20 verfügbar
Foto des Verkäufers
Cost-effective Methods for High-speed Nanometer CMOS VLSI Design
Verlag:
LAP LAMBERT Academic Publishing Mai 2010, 2010
ISBN 10: 3838307321
ISBN 13: 9783838307329
Neu
Taschenbuch
Anbieter: buchversandmimpf2000, Emtmannsberg, BAYE, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Taschenbuch. Zustand: Neu. Neuware -The semiconductor industry has been following Moore¿s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.Books on Demand GmbH, Überseering 33, 22297 Hamburg 132 pp. Englisch. Bestandsnummer des Verkäufers 9783838307329
Anzahl: 2 verfügbar
Foto des Verkäufers
Cost-effective Methods for High-speed Nanometer CMOS VLSI Design : Interconnect and Circuits
Verlag:
LAP LAMBERT Academic Publishing, 2009
ISBN 10: 3838307321
ISBN 13: 9783838307329
Neu
Taschenbuch
Anbieter: AHA-BUCH GmbH, Einbeck, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Taschenbuch. Zustand: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The semiconductor industry has been following Moore s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs. Bestandsnummer des Verkäufers 9783838307329
Anzahl: 1 verfügbar
Beispielbild für diese ISBN
Cost-effective Methods for High-speed Nanometer CMOS VLSI Design: Interconnect and Circuits
Verlag:
LAP Lambert Academic Publishing, 2009
ISBN 10: 3838307321
ISBN 13: 9783838307329
Gebraucht
Paperback
Anbieter: Mispah books, Redhill, SURRE, Vereinigtes Königreich
Verkäuferbewertung 4 von 5 Sternen
Paperback. Zustand: Like New. Like New. book. Bestandsnummer des Verkäufers ERICA79038383073216
Anzahl: 1 verfügbar