Low Power Flash ADC: VLSI Technology - Softcover

Subba Reddy, Murra

 
9783845440842: Low Power Flash ADC: VLSI Technology

Inhaltsangabe

In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.

Die Inhaltsangabe kann sich auf eine andere Ausgabe dieses Titels beziehen.

Reseña del editor

In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.

Biografía del autor

It describes how to design a low power flash ADC which gives high speed,low cost&less complexity rather than conventional flash ADC.

„Über diesen Titel“ kann sich auf eine andere Ausgabe dieses Titels beziehen.