Turbo decoder is a key component of the emerging 3G mobile communication. The focus of this work is towards developing an application specific integrated circuit for an advanced turbo decoder. The methodology starts from RTL models which can be used for software solution and proceeds towards hardware implementation. In the current project work, Turbo encoder and turbo decoder with SOVA and log-MAP decoding algorithms were modelled from algorithmic level, concentrating on the functional correctness rather than on implementation architecture. The effect on performance due to variation in parameters like frame length, number of iterations, type of encoding scheme and type of the interleaver in the presence of additive white Gaussian noise, using MATLAB. The hardware of the Turbo decoder has been modelled in VHDL, simulated in VCS, synthesized using Design compiler and physical implementation has been carried out using IC Compiler.
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Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Venkatesh Naresh KumarI have completed M.Sc [Engineering] VLSI System Design at M.S. Ramaiah School of Advanced Studies, Bangalore.Turbo decoder is a key component of the emerging 3G mobile communication. The focus of this work i. Bestandsnummer des Verkäufers 5509060
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Taschenbuch. Zustand: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Turbo decoder is a key component of the emerging 3G mobile communication. The focus of this work is towards developing an application specific integrated circuit for an advanced turbo decoder. The methodology starts from RTL models which can be used for software solution and proceeds towards hardware implementation. In the current project work, Turbo encoder and turbo decoder with SOVA and log-MAP decoding algorithms were modelled from algorithmic level, concentrating on the functional correctness rather than on implementation architecture. The effect on performance due to variation in parameters like frame length, number of iterations, type of encoding scheme and type of the interleaver in the presence of additive white Gaussian noise, using MATLAB. The hardware of the Turbo decoder has been modelled in VHDL, simulated in VCS, synthesized using Design compiler and physical implementation has been carried out using IC Compiler. Bestandsnummer des Verkäufers 9783847308553
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Taschenbuch. Zustand: Neu. Efficient Hardware Implementation of an Advanced Turbo Decoder | An ASIC Implementation | Naresh Kumar Venkatesh | Taschenbuch | Englisch | LAP Lambert Academic Publishing | EAN 9783847308553 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Bestandsnummer des Verkäufers 106525796
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