Digital PLL for Audio Applications: Based on ASIC Low Power and FPGA flow - Softcover

K Narayanan, Shesharaman

Softcover

ISBN 10: 3848404516 ISBN 13: 9783848404513

Verlag: LAP LAMBERT Academic Publishing, 2012

Über diesen Titel

Reseña del editor

In this project, Verilog HDL is used for the implementation due to its compatibility with pure digital hardware like FPGA's. The Digital PLL is simulated and verified on FPGA to experience its advantages. The circuit comprises of a phase detector, loop filter, Numerically Controlled Oscillator (NCO), and two clock dividers. The circuit was stabilized to produce the frequency in the audio frequency range of 9.7 KHz. This agreed with the classical phase-locked loop model for the system. The stable long-term frequency clock was verified on the FPGA to generate the required locking frequency. The DC logic synthesis and a new synopsis low power flow was experimented for back annotation and to obtain the maximum possible operating frequency and area, timing and power estimation.

Biografía del autor

Shesharaman K.N received the B.E. degree in Electronics and Communication Engineering from Visvesvaraya Technological University,Karnataka, India in 2005 and M.Sc[Engg.] degree in VLSI System Design from Coventry University,U.K in 2007. His present research is focused on Analog, Mixed mode VLSI design and Data Converters for Medical Applications

Details zur Ausgabe

• Verlag: LAP LAMBERT Academic Publishing
• Erscheinungsdatum: 2012
• ISBN 10: 3848404516
• ISBN 13: 9783848404513
• Einband: Tapa blanda
• Sprache: Englisch
• Anzahl der Seiten: 76