A HDL & Verilog Code: Simulated Output - Softcover

Sudhan, Manu; S., Manjunatha

 
9783848423248: A HDL & Verilog Code: Simulated Output
Softcover
ISBN 10: 3848423243 ISBN 13: 9783848423248
Verlag: LAP LAMBERT Academic Publishing, 2012

Inhaltsangabe

In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation. HDLs are standard text-based expressions of the spatial and temporal structure and behaviour of electronic systems. Like concurrent programming languages, HDL syntax and semantics includes explicit notations for expressing concurrency. However, in contrast to most software programming languages, HDLs also include an explicit notion of time, which is a primary attribute of hardware. Languages whose only characteristic is to express circuit connectivity between hierarchies of blocks are properly classified as netlist languages used on electric computer-aided design (CAD).

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Über die Autorin bzw. den Autor

B S Manusudhan/ECE/ATME College of Engineering,best academic achievement awardee.Core inventor of CBICT .Published many research papers in national & international level.Working on VLSI domain for designing "ATME-P2011" Processor.

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Verlag
LAP LAMBERT Academic Publishing
Erscheinungsdatum
2012
Sprache
Englisch
ISBN 10 
3848423243
ISBN 13 
9783848423248
Einband
Taschenbuch
Anzahl der Seiten
132
Kontakt zum Hersteller
Nicht verfügbar
Verantwortliche Person
Editions Vie
customerservice@vdm-vsg.de

Brivibas gatve 197
Riga
1039
Lettland