The field of ANN is moving forward in the domain of image processing especially for image compression and image enhancement. Software implementation of neural network architecture lacks the efficiency for commercial products, as they constrain the speed, increase area and predominantly the power. Hence there is always a need in developing mapping complex neural network architectures for image compression on hardware platforms. Hardware implementation of any complex architecture for commercial applications should be emphasized on reduction in power. Multi Layer Perceptron Neural Network structures have massive complex internal architectures, require more number of arithmetic units and consume large amount of power and area. Thus, power optimization techniques are needed to be designed. This can be possible either at architecture level or at algorithmic level or at physical level.The main objective of this research work is to design and optimize image compression algorithms using neural networks, and which should be compatible with hardware platforms for efficient implementation of these architectures with FPGA & ASIC.
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Dr M. Lakshmi Kiran is working as an Associate Professor in the Department of ECE at SRIT (Autonomous), Anantapuramu. The author published 8 research papers in reputed international journals and conferences. Research interests: in VLSI, DIP and Communication Systems. Dr Kiran has 8 years of teaching experience & 4 years of research experience.
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Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The field of ANN is moving forward in the domain of image processing especially for image compression and image enhancement. Software implementation of neural network architecture lacks the efficiency for commercial products, as they constrain the speed, increase area and predominantly the power. Hence there is always a need in developing mapping complex neural network architectures for image compression on hardware platforms. Hardware implementation of any complex architecture for commercial applications should be emphasized on reduction in power. Multi Layer Perceptron Neural Network structures have massive complex internal architectures, require more number of arithmetic units and consume large amount of power and area. Thus, power optimization techniques are needed to be designed. This can be possible either at architecture level or at algorithmic level or at physical level.The main objective of this research work is to design and optimize image compression algorithms using neural networks, and which should be compatible with hardware platforms for efficient implementation of these architectures with FPGA & ASIC. 120 pp. Englisch. Bestandsnummer des Verkäufers 9786138934769
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Kartoniert / Broschiert. Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Mukkara Lakshmi KiranDr M. Lakshmi Kiran is working as an Associate Professor in the Department of ECE at SRIT (Autonomous), Anantapuramu. The author published 8 research papers in reputed international journals and conferences. Res. Bestandsnummer des Verkäufers 389068264
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Taschenbuch. Zustand: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The field of ANN is moving forward in the domain of image processing especially for image compression and image enhancement. Software implementation of neural network architecture lacks the efficiency for commercial products, as they constrain the speed, increase area and predominantly the power. Hence there is always a need in developing mapping complex neural network architectures for image compression on hardware platforms. Hardware implementation of any complex architecture for commercial applications should be emphasized on reduction in power. Multi Layer Perceptron Neural Network structures have massive complex internal architectures, require more number of arithmetic units and consume large amount of power and area. Thus, power optimization techniques are needed to be designed. This can be possible either at architecture level or at algorithmic level or at physical level.The main objective of this research work is to design and optimize image compression algorithms using neural networks, and which should be compatible with hardware platforms for efficient implementation of these architectures with FPGA & ASIC.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 120 pp. Englisch. Bestandsnummer des Verkäufers 9786138934769
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Taschenbuch. Zustand: Neu. VLSI Architectures for Image Compression Applications | Implementing Image Processing with FPGA | Lakshmi Kiran Mukkara (u. a.) | Taschenbuch | 120 S. | Englisch | 2020 | Scholars' Press | EAN 9786138934769 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu. Bestandsnummer des Verkäufers 118786545
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Taschenbuch. Zustand: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The field of ANN is moving forward in the domain of image processing especially for image compression and image enhancement. Software implementation of neural network architecture lacks the efficiency for commercial products, as they constrain the speed, increase area and predominantly the power. Hence there is always a need in developing mapping complex neural network architectures for image compression on hardware platforms. Hardware implementation of any complex architecture for commercial applications should be emphasized on reduction in power. Multi Layer Perceptron Neural Network structures have massive complex internal architectures, require more number of arithmetic units and consume large amount of power and area. Thus, power optimization techniques are needed to be designed. This can be possible either at architecture level or at algorithmic level or at physical level.The main objective of this research work is to design and optimize image compression algorithms using neural networks, and which should be compatible with hardware platforms for efficient implementation of these architectures with FPGA & ASIC. Bestandsnummer des Verkäufers 9786138934769
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