Low Power Asynchronous Logic design for Viterbi Decoders - Softcover

Sakthivel, T. Kalavathi Devi; Palaniappan, Sakthivel

 
9786139851294: Low Power Asynchronous Logic design for Viterbi Decoders
Softcover
ISBN 10: 6139851297 ISBN 13: 9786139851294
Verlag: LAP LAMBERT Academic Publishing, 2018

Inhaltsangabe

This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation.

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Über die Autorin bzw. den Autor

Dr T. Kalavathi Devi completed her UG and PG in GCT, Coimbatore. Her areas of interest include VLSI Design, low power circuits, electronics system design. She has published papers in reputed journals and international conferences. She is a recipient of Best project guide award from ISTE New Delhi, also best researcher award from ASDF.

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Verlag
LAP LAMBERT Academic Publishing
Erscheinungsdatum
2018
Sprache
Englisch
ISBN 10 
6139851297
ISBN 13 
9786139851294
Einband
Taschenbuch
Anzahl der Seiten
56
Kontakt zum Hersteller
Nicht verfügbar
Verantwortliche Person
Edicoes Nosso Conhecimento
customerservice@vdm-vsg.de

SIA
Riga
1039
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