ASIC Implementation of Pezaris Multiplier in DIT FFT Architectures - Softcover

Karunamurthi, Saranya; Bojan, Vinoth Kumar; Ramachandran, Baby Janagam

 
9786139900619: ASIC Implementation of Pezaris Multiplier in DIT FFT Architectures
Softcover
ISBN 10: 6139900611 ISBN 13: 9786139900619
Verlag: LAP LAMBERT Academic Publishing, 2018

Inhaltsangabe

Multipliers with large bit lengths have a major impact on the performance of digital circuits in many applications like cryptography, digital signal processing and image processing. The performances of many computational problems are often dominated by the speed at which a multiplication operation can be executed. This book gives a brief overview of various multipliers such as Baugh Wooley, Pezaris, Array, Booth, Vedic multipliers and Compressor based multipliers. The main objective is to compare various types of multiplier in terms of power consumption, area and delay. These signed multiplication concepts are implemented in Verilog HDL and implemented in Cadence RTL Compiler with 180nm technology.

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Über die Autorin bzw. den Autor

Mrs. Saranya Karunamurthi is working as an Assistant Professor, Department of EEE in Dr. Mahalingam College of Engineering & Technology, Pollachi, Tamil Nadu, India. She completed her Master Degree in Applied Electronics under Anna University. Her research interests are VLSI Design, Analog & Digital Circuits, Reversible logics, ASIC Implementation.

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Verlag
LAP LAMBERT Academic Publishing
Erscheinungsdatum
2018
Sprache
Englisch
ISBN 10 
6139900611
ISBN 13 
9786139900619
Einband
Taschenbuch
Anzahl der Seiten
52
Kontakt zum Hersteller
Nicht verfügbar
Verantwortliche Person
Wydawnictwo Bezkresy Wiedzy
customerservice@vdm-vsg.de

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