In the design of VLSI, where an improvement in minimum supply voltage and a change in few Pico seconds of memory access or cycle times will make a big impact on SoC designs performance. SRAM cell write-ability and read stability are of prime concern at low supply voltages and also for process, voltage and temperature variations. When low supply voltage is applied to SRAM cell, the write operation will not be performed because the cell will not flip to desired voltage levels. A write assist circuit using a negative bitline voltage technique which can assist SRAM cell to flip to the desired voltage levels and assists the write operation is proposed for reducing write failures at low supply voltages.When low supply voltage applied to SRAM cell the read operation will not be performed in the selected cell and the cell stored data will be disturbed in the unselected cells. The proposed lowered WL voltage read assist circuit technique prevents the data from getting disturbed in unselected cells and also assists the read operation in selected cell.
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A. Pulla Reddy, Associate Professor, Dept. of ECE. He has 12 years of teaching experience. His research area of interests includes Digital and Analog Electronic Circuits.Prof.G. Sreenivasulu, Professor, Dept. of ECE. He has more than 20 years of teaching and research experience. His research area of interests includes Analog and Digital Circuits.
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Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. In the design of VLSI, where an improvement in minimum supply voltage and a change in few Pico seconds of memory access or cycle times will make a big impact on SoC designs performance. SRAM cell write-ability and read stability are of prime concern at low . Bestandsnummer des Verkäufers 1271252062
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Taschenbuch. Zustand: Neu. This item is printed on demand - Print on Demand Titel. Neuware -In the design of VLSI, where an improvement in minimum supply voltage and a change in few Pico seconds of memory access or cycle times will make a big impact on SoC designs performance. SRAM cell write-ability and read stability are of prime concern at low supply voltages and also for process, voltage and temperature variations. When low supply voltage is applied to SRAM cell, the write operation will not be performed because the cell will not flip to desired voltage levels. A write assist circuit using a negative bitline voltage technique which can assist SRAM cell to flip to the desired voltage levels and assists the write operation is proposed for reducing write failures at low supply voltages.When low supply voltage applied to SRAM cell the read operation will not be performed in the selected cell and the cell stored data will be disturbed in the unselected cells. The proposed lowered WL voltage read assist circuit technique prevents the data from getting disturbed in unselected cells and also assists the read operation in selected cell.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 120 pp. Englisch. Bestandsnummer des Verkäufers 9786206844730
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Taschenbuch. Zustand: Neu. SRAM Design in Nanometer Technologies | Low Voltage SRAM Circuit Techniques | Pulla Reddy A (u. a.) | Taschenbuch | Englisch | 2023 | LAP LAMBERT Academic Publishing | EAN 9786206844730 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Bestandsnummer des Verkäufers 128081685
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Taschenbuch. Zustand: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In the design of VLSI, where an improvement in minimum supply voltage and a change in few Pico seconds of memory access or cycle times will make a big impact on SoC designs performance. SRAM cell write-ability and read stability are of prime concern at low supply voltages and also for process, voltage and temperature variations. When low supply voltage is applied to SRAM cell, the write operation will not be performed because the cell will not flip to desired voltage levels. A write assist circuit using a negative bitline voltage technique which can assist SRAM cell to flip to the desired voltage levels and assists the write operation is proposed for reducing write failures at low supply voltages.When low supply voltage applied to SRAM cell the read operation will not be performed in the selected cell and the cell stored data will be disturbed in the unselected cells. The proposed lowered WL voltage read assist circuit technique prevents the data from getting disturbed in unselected cells and also assists the read operation in selected cell. Bestandsnummer des Verkäufers 9786206844730
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