OFDM is mainly used to transmit video and audio signals efficiently with high performance and speed. FFT has various applications in, digital signal processing, and biomedical applications. There is a demand for semiconductor technology in terms of high performance, low area and power consumption. This increasing power is a significant problem in current processing communication technology. Therefore, various low-power FFT processors are designed to maximise the system life and meet consumer demand by extending the battery life at a lower cost. In this thesis, FFT processor is designed by using optimized radix 2 DIT butterfly structure with proposed floating point adders and floating point multipliers. The performance of the proposed binary floating point Vedic multiplier is compared with existing floating point multipliers with different adders. The designed cached FFT processor using radix 26 algorithm with SDF pipeline architecture, compared the performance parameters like area, power and operating frequency with existing pipeline architectures. We demonstrated that our proposed Binary floating point Vedic multiplier in Cached radix 26 SDF FFT achieves better power consumption.
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C Padma, Ph.D., currently working as Associate Professor in the department of ECE, Sri Venkateswara Engineering College, Tirupati, Andhra Pradesh. she recived her Ph.D Degree in VLSI and Signal Processing in 2023 from JNTUA, Ananthapuramu. She has 13 years of Teaching Experience. Her research interest includes, VLSI, Signal Processing and IOT.
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Taschenbuch. Zustand: Neu. Implementation of FFT Processor In Nanometer Technologies | Low Power Design Methodologies of FFT Processor | Padma Challa (u. a.) | Taschenbuch | Einband - flex.(Paperback) | Englisch | 2024 | LAP LAMBERT Academic Publishing | EAN 9786208224608 | Verantwortliche Person für die EU: SIA OmniScriptum Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu. Bestandsnummer des Verkäufers 130657514
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Taschenbuch. Zustand: Neu. Neuware -OFDM is mainly used to transmit video and audio signals efficiently with high performance and speed. FFT has various applications in, digital signal processing, and biomedical applications. There is a demand for semiconductor technology in terms of high performance, low area and power consumption. This increasing power is a significant problem in current processing communication technology. Therefore, various low-power FFT processors are designed to maximise the system life and meet consumer demand by extending the battery life at a lower cost. In this thesis, FFT processor is designed by using optimized radix 2 DIT butterfly structure with proposed floating point adders and floating point multipliers. The performance of the proposed binary floating point Vedic multiplier is compared with existing floating point multipliers with different adders. The designed cached FFT processor using radix 26 algorithm with SDF pipeline architecture, compared the performance parameters like area, power and operating frequency with existing pipeline architectures. We demonstrated that our proposed Binary floating point Vedic multiplier in Cached radix 26 SDF FFT achieves better power consumption.Books on Demand GmbH, Überseering 33, 22297 Hamburg 144 pp. Englisch. Bestandsnummer des Verkäufers 9786208224608
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