DESIGN OF RISC V FIVE STAGE PROCESSOR USING VERILOG - Softcover

S, Darshan; K, Jagan; S, Darshini

Softcover

ISBN 10: 6209823181 ISBN 13: 9786209823183

Verlag: LAP LAMBERT Academic Publishing, 2026

Inhaltsangabe

This project presents the design and simulation of a RISC-V 5-stage pipelined processor based on the Reduced Instruction Set Computing (RISC) architecture. The processor operates through five stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB), enabling instruction-level parallelism and improved performance. The design is implemented using Verilog HDL and includes key modules such as the Program Counter, Instruction Memory, Register File, Immediate Generator, ALU, Data Memory, Pipeline Registers, and Control Unit. The ALU Control Unit interprets funct3 and funct7 fields to generate required operations, while the main controller ensures proper control signal flow. Hazard detection and data forwarding units are incorporated to handle pipeline hazards effectively. Functional verification using testbench simulations confirms correct instruction execution and register updates. This modular design supports scalability, with future enhancements including branch prediction, cache integration, and FPGA-based real-time implementation.

Über diesen Titel

Über die Autorin bzw. den Autor

Mr. Darshan S is a final-year B.E. ECE student passionate about VLSI and semiconductor technology. He specializes in digital design, HDL coding, and low-power architectures, with hands-on experience in Verilog, FPGA implementation, and physical design, aiming for a career in chip design.

Details zur Ausgabe

• Verlag: LAP LAMBERT Academic Publishing
• Erscheinungsdatum: 2026
• Sprache: Englisch
• ISBN 10: 6209823181
• ISBN 13: 9786209823183
• Einband: Taschenbuch
• Anzahl der Seiten: 56
• Kontakt zum Hersteller: SIA OmniScriptum Publishing; customerservice@vdm-vsg.de; ; Brivibas gatve 197; Riga; 1039; Lettland