EUR 16,00 für den Versand von China nach USA
Versandziele, Kosten & DauerAnbieter: liu xing, Nanjing, JS, China
paperback. Zustand: New. Paperback. Pub Date: 2005 Pages: 710 Language: Chinese in Publisher: Electronic Industry Press book explained by a large number of complete instances the use VerilogHDL VLSI design structured modeling method. key steps and design verification method and other useful content. The book is divided into 11 chapters. covering modeling. structural balance. functional verification. fault simulation. and logic synthesis. and other key issues. as well as after the comprehensive design validation. timi. Bestandsnummer des Verkäufers CB022334
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Anbieter: dsmbooks, Liverpool, Vereinigtes Königreich
paperback. Zustand: New. New. book. Bestandsnummer des Verkäufers D8S0-3-M-7505399179-6
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