Advanced ASIC Chip Synthesis: Using Synopsysa (R) Design Compilera (R) and Primetimea (R)

Bhatnagar, Himanshu

ISBN 10: 0792385373 / ISBN 13: 9780792385370

Verlag: Kluwer Academic Publishers, 1999

Beschreibung

Former library book; May have limited writing in cover pages. Pages are unmarked. ~ ThriftBooks: Read More, Spend Less 1.45.

Bestandsnummer des Verkäufers G0792385373I4N10

Bibliografische Details

• Titel: Advanced ASIC Chip Synthesis: Using Synopsysa (R) Design Compilera (R) and Primetimea (R)
• Verlag: Kluwer Academic Publishers
• Erscheinungsjahr: 1999
• Sprache: Englisch
• ISBN-10: 0792385373
• ISBN-13: 9780792385370
• Einband: Hardcover
• Zustand: Very Good
• Zustand des Schutzumschlags: No Jacket

Über diesen Titel

Inhaltsangabe

Foreword. Preface. Acknowledgements. About the Author. 1. ASIC Design Methodology. 2. Tutorial. 3. Basic Concepts. 4. Synopsys Technology Library. 5. Partitioning and Coding Styles. 6. Constraining Designs. 7. Optimizing Designs. 8. Design for Test. 9. Links to Layout & Post-Layout Optimization. 10. SDF Generation. 11. PrimeTime Basics. 12. Static Timing Analysis. Appendix. Index.

Reseña del editor

This text describes the advanced concepts and techniques used for ASIC chip synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of Synopsys tools used to combat various problems seen at VDSM geometries. Readers are exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-arounds described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. The book is intended for anyone who is involved in the ASIC design methodology, starting from RTL synthesis to final tape-out. Target audiences for this book are practicing ASIC design engineers and graduate students undertaking advanced courses in ASIC chip design and DFT techniques.