Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)

Gangadharan, Sridhar; Churiwala, Sanjay

ISBN 10: 1461432685 / ISBN 13: 9781461432685

Verlag: Springer, 2013

Beschreibung

Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Acceptable condition! Any other included accessories are also in Acceptable condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear such as cover tears discoloration, staining, marks, scuffs, etc. All pages intact.

Bestandsnummer des Verkäufers GWSVV.1461432685.A

Bibliografische Details

• Titel: Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)
• Verlag: Springer
• Erscheinungsjahr: 2013
• Sprache: Englisch
• ISBN-10: 1461432685
• ISBN-13: 9781461432685
• Einband: Hardcover
• Zustand: acceptable

Über diesen Titel

Inhaltsangabe

This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.

Über die Autorin bzw. den Autor

Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, with two decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx.

Sridhar Gangadharan  is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass  RTL Analysis Products at Atrenta. He has over 20 years of experience in the electronic design automation industry. His interest areas include RTL verification, timing closure, delay calculation and memory compilers. He holds a Bachelors degree in Computer Science and Engineering from Indian Institute of Technology in Delhi. He is based in San Jose, CA.