ADVANCEMENTS IN SMALL-PIXEL, VIDEO-RATE, BACKSIDE-ILLUMINATED CHARGE-COUPLED DEVICES

John R. Tower

Samoff Corporation CN 5300 Princeton, NJ 08540-5300

1 ABSTRACT

Sarnoff Corporation has developed a CMOS-CCD process technology that has enabled the development of a new generation of backside-illuminated charge-coupled devices (CCDs). The new devices achieve high quantum efficiency (QE), combined with high modulation transfer function (MTF) performance, at pixel sizes down to 6.6 microns. This new generation of CCDs also provides excellent noise performance at video readout rates. To permit the realization of large-format devices, photocomposition (stitching) has also been demonstrated within this new process technology.

2 INTRODUCTION

Sarnoff, formerly RCA Laboratories, began work on CCD development in 1971. The backside-illuminated CCD work at RCA dates back to 1978. The backside-illuminated process that has now been employed for over twenty years utilizes whole wafer thinning with backside lamination to a glass support substrate. The back surface is implanted and then furnace annealed to provide stable, high quantum efficiency from < 400nm to > 1,000 nm.

Over the past few years, Samoff has been moving toward a more unified processing approach across our imaging products. Recently, we have integrated aspects of our double polysilicon spectroscopic CMOS-CCD process with our backside-illuminated, triple polysilicon CCD process. We have also moved the majority of our products to Canon 5X lithography to achieve tighter design rules. This paper will summarize the present state-of-the-art at Sarnoff.

3 PROCESS TECHNOLOGY

The new generation of backside-illuminated devices is processed in a triple polysilicon, single-level metal process technology with aluminum metallization. The process technology supports full CMOS circuitry in a twin well configuration. Standard oxide thicknesses are employed for pixel sizes > 12 microns, and scaled, thin oxides are employed for pixel sizes < 12 microns. The CMOS/CCD process supports CMOS-quality electrostatic discharge (ESD) pad protection.

A number of process options have been incorporated into the process flow. Pixel or horizontal register buried blooming drain structures can be implemented to achieve anti-blooming. Buried contacts can be realized to reduce the floating diffusion capacitance. This floating diffusion stray capacitance reduction increases the output sensitivity and reduces the amplifier equivalent noise.

To achieve high-speed clocking of vertical register gates, metal-to-poly strapping contacts have been demonstrated for pixel sizes down to 8 microns. These small geometry contacts are the enabling technique for achieving 1 MHz vertical clock rates on CCDs with > 50-mm-long gates at an 8-micron pixel pitch.

To produce very long linear array devices, Sarnoff has developed photocomposition (stitching) capability on the Canon 5X stepper. Employing stitching, Sarnoff has demonstrated > 60-mm-long devices. Figure 1 shows a long linear array produced with stitching. Figure 2 shows the excellent registration and feature size fidelity achieved with stitching. The figure indicates the stitch boundary location. The poly 2 gates at the top of the figure are 4 microns in width. The stitch boundary is difficult to detect, with typical panel-to-panel misalignments of 0.1 micron.

4 IMPROVEMENTS IN QUANTUM EFFICIENCY

The major advantage of backside illumination is the high quantum efficiency that can be achieved, particularly at wavelengths below 550 nm. With 100% optical fill factor and no gates to absorb short wavelength photons, backside-illuminated devices can approach ideal silicon quantum efficiency. Figure 3 indicates measured QE for the best non-AR coated devices peaking at 80%. With the AR coatings now being developed, the peak QE should be > 90%. Furthermore, as indicated in Figure 3, the AR coatings can be tailored to peak the QE in the band of interest.

5 IMPROVEMENTS IN DYNAMIC RANGE

As the pixel size is reduced, the dynamic range is compressed due to reduction in full well capacity. To maximize the dynamic range for small pixel devices we have 1) increased the area charge capacity (e/µm2) of the pixel, and 2) decreased the amplifier noise floor. The measured improvement in full well will be discussed first. Two small pixel designs have been fabricated with standard buried channel implants and enhanced, high capacity implants. The measured full-well results are indicated in Table 1. The criteria for full well is the maximum charge that can be transferred without extended-edge-response charge-transfer efficiency (CTE) degradation. The Nova 8-micron pixel results indicate that > 1.5 X improvement in full well can be achieved moving from the standard implant to the high capacity implants. The charge density is > 9,000 e/µm2 for the improved Nova device. The Mark V 6.6-micron pixel design does not exhibit charge densities as high as the Nova design. By layout changes, the design can be optimized further to provide higher charge capacity. However, as is, this charge capacity is excellent for such a small pixel device.

To achieve a full...