An Efficient Implementation of High-Speed JPEG2000 Encoder/Decoder

Michael Yaw Appiah

ISBN 10: 3838334760 / ISBN 13: 9783838334769

Verlag: LAP LAMBERT Academic Publishing Dez 2009, 2009

Beschreibung

This item is printed on demand - it takes 3-4 days longer - Neuware -This book presents a complete and up-to-date description of an efficient FPGA implementation of high-speed JPEG2000 using formal design methodologies namely SpecC and A3, in a systematic and clear manner. JPEG2000 proposes a large set of advanced features for today's internet and multimedia applications. At the heart of JPEG2000 are two complex DSP algorithms: Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optmized Truncation (EBCOT). Both algorithms are complex, compute intensive and very difficult to optimize in software implementation for real-time imaging and multimedia applications. A hardware implementation brings a solution to this complexity for real-time applications. This book proposes flexible and efficient architectures for DWT, matching arithmetic coder (MQ coder) and EBCOT units of the JPEG2000 system. The implemented parallel structure increases throughput off the Tier-1 (EBCOT and MQC) and DWT by factors of 301 and 164 cycles respectively. Execution results from software only and FPGA implemented JPEG2000 is compared and analyzed. 128 pp. Englisch.

Bestandsnummer des Verkäufers 9783838334769

Bibliografische Details

• Titel: An Efficient Implementation of High-Speed JPEG2000 Encoder/Decoder
• Verlag: LAP LAMBERT Academic Publishing Dez 2009
• Erscheinungsjahr: 2009
• Sprache: Englisch
• ISBN-10: 3838334760
• ISBN-13: 9783838334769
• Einband: Taschenbuch
• Zustand: Neu

Über diesen Titel

Inhaltsangabe

This book presents a complete and up-to-date description of an efficient FPGA implementation of high-speed JPEG2000 using formal design methodologies namely SpecC and A3, in a systematic and clear manner. JPEG2000 proposes a large set of advanced features for today's internet and multimedia applications. At the heart of JPEG2000 are two complex DSP algorithms: Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optmized Truncation (EBCOT). Both algorithms are complex, compute intensive and very difficult to optimize in software implementation for real-time imaging and multimedia applications. A hardware implementation brings a solution to this complexity for real-time applications. This book proposes flexible and efficient architectures for DWT, matching arithmetic coder (MQ coder) and EBCOT units of the JPEG2000 system. The implemented parallel structure increases throughput off the Tier-1 (EBCOT and MQC) and DWT by factors of 301 and 164 cycles respectively. Execution results from software only and FPGA implemented JPEG2000 is compared and analyzed.