This book aims to cover different aspects of Bias Temperature Instability (BTI). BTI remains as an important reliability concern for CMOS transistors and circuits. Development of BTI resilient technology relies on utilizing artefact-free stress and measurement methods and suitable physics-based models for accurate determination of degradation at end-of-life and understanding the gate insulator process impact on BTI. This book discusses different ultra-fast characterization techniques for recovery artefact free BTI measurements. It also covers different direct measurements techniques to access pre-existing and newly generated gate insulator traps responsible for BTI. The book provides a consistent physical framework for NBTI and PBTI respectively for p- and n- channel MOSFETs, consisting of trap generation and trapping. A physics-based compact model is presented to estimate measured BTI degradation in planar Si MOSFETs having differently processed SiON and HKMG gate insulators, in planar SiGe MOSFETs and also in Si FinFETs. The contents also include a detailed investigation of the gate insulator process dependence of BTI in differently processed SiON and HKMG MOSFETs. The book then goes on to discuss Reaction-Diffusion (RD) model to estimate generation of new traps for DC and AC NBTI stress and Transient Trap Occupancy Model (TTOM) to estimate charge occupancy of generated traps and their contribution to BTI degradation. Finally, a comprehensive NBTI modeling framework including TTOM enabled RD model and hole trapping to predict time evolution of BTI degradation and recovery during and after DC stress for different stress and recovery biases and temperature, during consecutive arbitrary stress and recovery cycles and during AC stress at different frequency and duty cycle. The contents of this book should prove useful to academia and professionals alike.
Souvik Mahapatra received his Bachelors and Masters degrees in Physics from Jadavpur University, Calcutta, India in 1993 and 1995 respectively and PhD in Electrical Engineering from IIT Bombay, Mumbai, India in 1999. During 2000-2001, he was with Bell Laboratories, Lucent Technologies, Murray Hill, NJ, USA. Since 2002 he is with the Department of Electrical Engineering at IIT Bombay and currently holds the position of full professor. His primary research interests are in the area of semiconductor device characterization, modeling and simulation and in particular, MOS transistor and Flash memory device scaling and reliability. He has contributed in several technologically relevant research areas such as MOS gate insulator scaling, Channel Hot Carrier Degradation and Bias Temperature Instability in CMOS devices and CHISEL NOR Flash, SONOS NOR and NAND Flash and Metal Nanodot NAND Flash memory devices. He has published more than 150 papers in peer reviewed journals and conferences, delivered invited talks and tutorials in major international conferences including at the IEEE IEDM and IEEE IRPS and served as a committee member and session chair in several IEEE conferences. He is a fellow of the Indian National Academy of Engineering, senior member of IEEE and a distinguished lecturer of IEEE EDS.
