Hardware Support for Efficient Transactional Memory Systems : Hardware Techniques for High-Performance Transactional Memory in Many-Core Chip Multiprocessors

Ruben Titos-Gil

ISBN 10: 3847336525 / ISBN 13: 9783847336525

Verlag: LAP LAMBERT Academic Publishing, 2012

Beschreibung

nach der Bestellung gedruckt Neuware - Printed after ordering - The rise of multicores has brought the problem of effective concurrent programming to the forefront of computing research, presenting both immense opportunities and enormous challenges. Traditional multithreaded programming models use low-level primitives such as locks to guarantee mutual exclusion and protect shared data. The trade-off between programming ease and performance imposed by locks remains one of the key challenges to programmers and computer architects of the multicore era. Transactional Memory (TM) is a conceptually simpler programming model that can help boost developer productivity by eliminating the complex task of reasoning about the intricacies of safe fine-grained locking. Fast implementations of transactional programming constructs are necessary for TM to gain widespread usage. This book focuses on the hardware mechanisms that provide optimistic concurrency control with stringent guarantees of atomicity and isolation, with the intent of achieving high-performance across a variety of workloads, at a reasonable cost in terms of design complexity. Bestandsnummer des Verkäufers 9783847336525

Bibliografische Details

Titel: Hardware Support for Efficient Transactional...

Verlag: LAP LAMBERT Academic Publishing

Erscheinungsdatum: 2012

Einband: Taschenbuch

Zustand: Neu

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Reseña del editor:

The rise of multicores has brought the problem of effective concurrent programming to the forefront of computing research, presenting both immense opportunities and enormous challenges. Traditional multithreaded programming models use low-level primitives such as locks to guarantee mutual exclusion and protect shared data. The trade-off between programming ease and performance imposed by locks remains one of the key challenges to programmers and computer architects of the multicore era. Transactional Memory (TM) is a conceptually simpler programming model that can help boost developer productivity by eliminating the complex task of reasoning about the intricacies of safe fine-grained locking. Fast implementations of transactional programming constructs are necessary for TM to gain widespread usage. This book focuses on the hardware mechanisms that provide optimistic concurrency control with stringent guarantees of atomicity and isolation, with the intent of achieving high-performance across a variety of workloads, at a reasonable cost in terms of design complexity.