An invited talk recounts Intel's experience with increasing die yield through CAD algorithms, and a panel discussion examines tools for the extracting of critical areas for a yield analysis of VLSI design. Others of the 34 papers cover critical area analysis, defect sensitivity and reliability, fault tolerant architectures and arrays, yield projection and enhancement, fault tolerant and testing techniques, and self-checking and coding techniques. No subject index. Annotation copyright Book News, Inc. Portland, Or.

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Verwandte Artikel zu The IEEE international workshop on Defect & Fault-Tolera...

The IEEE international workshop on Defect & Fault-Tolerance in VLSI Systems, Proceedings, 1995.

IEEE Computer Society.

Gebraucht - Hardcover

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