This book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVerilog language. Readers will benefit from the step-by-step approach to learning the language and methodology nuances, which will enable them to design and verify complex ASIC/SoC and CPU chips. The author covers the entire spectrum of the language, including random constraints, SystemVerilog Assertions, Functional Coverage, Class, checkers, interfaces, and Data Types, among other features of the language. Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the complex task of multi-million gate ASIC designs.

Provides comprehensive coverage of the entire IEEE standard SystemVerilog language;
Covers important topics such as constrained random verification, SystemVerilog Class, Assertions, Functional coverage, data types, checkers, interfaces, processes and procedures, among other language features;
Uses easy to understand examples and simulation logs; examples are simulatable and will be provided online;
Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs.

This is quite a comprehensive work. It must have taken a long time to write it. I really like that the author has taken apart each of the SystemVerilog constructs and talks about them in great detail, including example code and simulation logs. For example, there is a chapter dedicated to arrays, and another dedicated to queues - that is great to have!

The Language Reference Manual (LRM) is quite dense and difficult to use as a text for learning the language. This book explains semantics at a level of detail that is not possible in an LRM. This is the strength of the book. This will be an excellent book for novice users and as a handy reference for experienced programmers.

Mark Glasser

Cerebras Systems

�ber die Autorin bzw. den Autor

Ashok Mehta is an ASIC/CPU design and verification engineer with over 30 years of experience in the semiconductor industry. He has worked at companies such as DEC, Data General, Intel, Applied Micro and TSMC. He was an early member of the Verilog technical subcommittees. He is the holder of 19 US Patents in the field of ASIC and 3DIC design and verification. He is also the author of two popular books, one on "SystemVerilog Assertions and Functional Coverage" and second on "ASIC Functional Design Verification – A guide to technologies and methodologies". His current interest include 3DIC semiconductor design verification, System Level Modeling (Virtual Platform) and verification methodologies in general.

��ber diesen Titel� kann sich auf eine andere Ausgabe dieses Titels beziehen.

Anbieterinformationen

Zur Homepage des Verk�ufers

Unternehmensdaten des Verk�ufers

Edward Bowditch Ltd
Exstowe, Exton, Exeter, EX3 0PP, United Kingdom

Gesch�ftsbedingungen und Versandinformationen

Verkaufsbedingungen

Legal entity name: Edward Bowditch Ltd
Legal entity form: Limited company
Business correspondence address: Exstowe, Exton, Exeter, EX3 0PP
Company registration number: 04916632
VAT registration: GB834241546
Authorised representative: Mr. E. Bowditch

Widerrufsbelehrung

Versandbedingungen

Orders usually dispatched within two working days.

Versandkosten von Vereinigtes K�nigreich nach USA

Versandkosten von Vereinigtes K�nigreich nach USA
Bestellmenge	7 bis 18�Werktage	2 bis 5�Werktage
Erster Artikel	EUR 28.75	EUR 28.75

Die Versandzeiten werden von den Verk�uferinnen und Verk�ufern festgelegt. Sie variieren je nach Versanddienstleister und Standort. Sendungen, die den Zoll passieren, k�nnen Verz�gerungen unterliegen. Eventuell anfallende Abgaben oder Geb�hren sind von der K�uferin bzw. dem K�ufer zu tragen. Die Verk�uferin bzw. der Verk�ufer kann Sie bez�glich zus�tzlicher Versandkosten kontaktieren, um einen m�glichen Anstieg der Versandkosten f�r Ihre Artikel auszugleichen.