Layout-Aware Analog Synthesis Methodology

Raoul Badaoui

ISBN 10: 3844304797 / ISBN 13: 9783844304794

Verlag: LAP LAMBERT Academic Publishing Mär 2011, 2011

Beschreibung

Neuware -Layout-induced parasitics have significant effects on the behavior of circuits in general and the performance of high-frequency analog ones in particular. To achieve parasite-inclusive performance-closure, layout-aware circuit synthesis methodologies are beginning to emerge. In layout-in-the-loop synthesis methodologies, performance analysis is based on the generation of a concrete layout for the explored circuit sizes. A parasite-inclusive circuit is extracted from the layout using a standard extractor and is analyzed using a simulator to determine whether the required constraints are met; this is time consuming. Various approaches of estimating parasitics lack the correctness that would only come from examining the layout itself. The proposed approach tries to include the exactness of the layout to be generated without actually generating it. It relies on using pre-generated structures for the specified unsized circuit; these structures are generated pre-synthesis and contain the information that a layout would have provided to a synthesis process if it was to be generated. This information contains extraction specifics for modules, their location and routing characteristics.Books on Demand GmbH, Überseering 33, 22297 Hamburg 176 pp. Englisch.

Bestandsnummer des Verkäufers 9783844304794

Bibliografische Details

• Titel: Layout-Aware Analog Synthesis Methodology
• Verlag: LAP LAMBERT Academic Publishing Mär 2011
• Erscheinungsjahr: 2011
• Sprache: Englisch
• ISBN-10: 3844304797
• ISBN-13: 9783844304794
• Einband: Taschenbuch
• Zustand: Neu
• Abmessungen: 220B x 150 H x 11 T Millimeter Breite: 220 mm, Höhe: 150 mm, Tiefe: 11 mm
• Gewicht: 280 Gramm

Über diesen Titel

Inhaltsangabe

Layout-induced parasitics have significant effects on the behavior of circuits in general and the performance of high-frequency analog ones in particular. To achieve parasite-inclusive performance-closure, layout-aware circuit synthesis methodologies are beginning to emerge. In layout-in-the-loop synthesis methodologies, performance analysis is based on the generation of a concrete layout for the explored circuit sizes. A parasite-inclusive circuit is extracted from the layout using a standard extractor and is analyzed using a simulator to determine whether the required constraints are met; this is time consuming. Various approaches of estimating parasitics lack the correctness that would only come from examining the layout itself. The proposed approach tries to include the exactness of the layout to be generated without actually generating it. It relies on using pre-generated structures for the specified unsized circuit; these structures are generated pre-synthesis and contain the information that a layout would have provided to a synthesis process if it was to be generated. This information contains extraction specifics for modules, their location and routing characteristics.