Logic Synthesis for Low Power VLSI Designs (Paperback)

Massoud Pedram

ISBN 10: 1461374901 / ISBN 13: 9781461374909

Verlag: Springer-Verlag New York Inc., New York, NY, 2012

Beschreibung

Paperback. Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints. Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis. Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability.

Bestandsnummer des Verkäufers 9781461374909

Bibliografische Details

• Titel: Logic Synthesis for Low Power VLSI Designs (Paperback)
• Verlag: Springer-Verlag New York Inc., New York, NY
• Erscheinungsjahr: 2012
• Sprache: Englisch
• ISBN-10: 1461374901
• ISBN-13: 9781461374909
• Einband: Paperback
• Zustand: new

Über diesen Titel

Inhaltsangabe

Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.