Logic Synthesis Using Synopsys

Kurup, Pran

ISBN 10: 0792395824 / ISBN 13: 9780792395829

Verlag: Kluwer Academic Publishers, 1995

Beschreibung

This is an ex-library book and may have the usual library/used-book markings inside.This book has hardback covers. In good all round condition. No dust jacket. Please note the Image in this listing is a stock photo and may not match the covers of the actual item,800grams, ISBN:9780792395829. Bestandsnummer des Verkäufers 4137487

Bibliografische Details

Titel: Logic Synthesis Using Synopsys

Verlag: Kluwer Academic Publishers

Erscheinungsdatum: 1995

Einband: Hardcover

Zustand: Good

Über diesen Titel

Inhaltsangabe:

Book by Kurup Pran Abbasi Taher

Reseña del editor:

Logic synthesis has become a fundamental component of the ASIC design flow, and Logic Synthesis Using Synopsys® has been written for all those who dislike reading manuals but who still like to learn logic synthesis as practised in the real world. The primary focus of the book is Synopsys Design Compiler®: the leading synthesis tool in the EDA marketplace. The book is specially organized to assist designers accustomed to schematic capture based design to develop the required expertise to effectively use the Compiler. Over 100 `classic scenarios' faced by designers using the Design Compiler have been captured and discussed, and solutions provided. The scenarios are based both on personal experiences and actual user queries. A general understanding of the problem-solving techniques provided will help the reader debug similar and more complicated problems. Furthermore, several examples and dc-shell scripts are provided.
Specifically, Logic Synthesis Using Synopsys® will help the reader develop a better understanding of the synthesis design flow, optimization strategies using the Design Compiler, test insertion using the Test Compiler®, commonly used interface formats such as EDIF and SDF, and design re-use in a synthesis-based design methodology. Examples have been provided in both VHDL and Verilog.
Audience: Written with CAD engineers in mind to enable them to formulate an effective synthesis-based ASIC design methodology. Will also assist design teams to better incorporate and effectively integrate synthesis with their existing in-house design methodology and CAD tools.