Logical Time @ Work for the Modeling and Analysis of Embedded Systems

Frederic Mallet

ISBN 10: 3843393885 / ISBN 13: 9783843393881

Verlag: LAP LAMBERT Academic Publishing Jan 2011, 2011

Beschreibung

This item is printed on demand - it takes 3-4 days longer - Neuware -Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise physical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented. 124 pp. Englisch.

Bestandsnummer des Verkäufers 9783843393881

Bibliografische Details

• Titel: Logical Time @ Work for the Modeling and Analysis of Embedded Systems
• Verlag: LAP LAMBERT Academic Publishing Jan 2011
• Erscheinungsjahr: 2011
• Sprache: Englisch
• ISBN-10: 3843393885
• ISBN-13: 9783843393881
• Einband: Taschenbuch
• Zustand: Neu

Über diesen Titel

Inhaltsangabe

Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise physical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented.

Über die Autorin bzw. den Autor

Dr. Eng. Habil. Frederic Mallet is an Associate Professor in the Computer Science department at Nice-Sophia Antipolis University. He is a member of the AOSTE research unit, a joint team between the I3S Laboratory and INRIA Sophia Antipolis research center. He is a voting member of the OMG revision task forces for MARTE and SysML UML Profiles.