Low Power Design With High-Level Power Estimation and Power-Aware Synthesis

Ahuja, Sumit/ Lakshminarayana, Avinash/ Shukla, Sandeep Kumar

ISBN 10: 1461408717 / ISBN 13: 9781461408710

Verlag: Springer Verlag, 2011

Beschreibung

170 pages. 9.25x6.50x0.75 inches. In Stock.

Bestandsnummer des Verkäufers x-1461408717

Bibliografische Details

• Titel: Low Power Design With High-Level Power Estimation and Power-Aware Synthesis
• Verlag: Springer Verlag
• Erscheinungsjahr: 2011
• Sprache: Englisch
• ISBN-10: 1461408717
• ISBN-13: 9781461408710
• Einband: Hardcover
• Zustand: Brand New
• Gewicht: 0,47 Kilogramm

Über diesen Titel

Inhaltsangabe

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

Von der hinteren Coverseite

Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phones, PDAs and high performance machines for data centers. To achieve short time to market, design flows must facilitate a much shortened time-to-product requirement. High-level modeling, architectural exploration and direct synthesis of design from high level description enable this design process.

This book presents novel research techniques, algorithms,methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

• Integrates power estimation and reduction for high level synthesis, with low-power, high-level design;
• Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives;
• Covers techniques from RTL/gate-level to hardware software co-design.